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Commit 1bcbf42d authored by Dan Williams's avatar Dan Williams
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nfit: fix format interface code byte order 

Per JEDEC Annex L Release 3 the SPD data is:

Bits 9~5 00 000 = Function Undefined
         00 001 = Byte addressable energy backed
         00 010 = Block addressed
         00 011 = Byte addressable, no energy backed
         All other codes reserved
Bits 4~0 0 0000 = Proprietary interface
         0 0001 = Standard interface 1
         All other codes reserved; see Definitions of Functions

...and per the ACPI 6.1 spec:

    byte0: Bits 4~0 (0 or 1)
    byte1: Bits 9~5 (1, 2, or 3)

...so a format interface code displayed as 0x301 should be stored in the
nfit as (0x1, 0x3), little-endian.

Cc: Toshi Kani <toshi.kani@hpe.com>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Robert Moore <robert.moore@intel.com>
Cc: Robert Elliott <elliott@hpe.com>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=121161


Fixes: 30ec5fd4 ("nfit: fix format interface code byte order per ACPI6.1")
Fixes: 5ad9a7fd ("acpi/nfit: Update nfit driver to comply with ACPI 6.1")
Reported-by: default avatarKristin Jacque <kristin.jacque@intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 02395435

drivers/acpi/nfit.c

+3 −3
Original line number Diff line number Diff line
@@ -928,7 +928,7 @@ static ssize_t format_show(struct device *dev, 
{

	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);



	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->code));

	return sprintf(buf, "0x%04x\n", le16_to_cpu(dcr->code));

}

static DEVICE_ATTR_RO(format);
@@ -961,8 +961,8 @@ static ssize_t format1_show(struct device *dev, 
				continue;

			if (nfit_dcr->dcr->code == dcr->code)

				continue;

			rc = sprintf(buf, "%#x\n",

					be16_to_cpu(nfit_dcr->dcr->code));

			rc = sprintf(buf, "0x%04x\n",

					le16_to_cpu(nfit_dcr->dcr->code));

			break;

		}

		if (rc != ENXIO)

drivers/acpi/nfit.h

+5 −5
Original line number Diff line number Diff line
@@ -53,12 +53,12 @@ enum nfit_uuids { 
};



/*

 * Region format interface codes are stored as an array of bytes in the

 * NFIT DIMM Control Region structure

 * Region format interface codes are stored with the interface as the

 * LSB and the function as the MSB.

 */

#define NFIT_FIC_BYTE cpu_to_be16(0x101) /* byte-addressable energy backed */

#define NFIT_FIC_BLK cpu_to_be16(0x201) /* block-addressable non-energy backed */

#define NFIT_FIC_BYTEN cpu_to_be16(0x301) /* byte-addressable non-energy backed */

#define NFIT_FIC_BYTE cpu_to_le16(0x101) /* byte-addressable energy backed */

#define NFIT_FIC_BLK cpu_to_le16(0x201) /* block-addressable non-energy backed */

#define NFIT_FIC_BYTEN cpu_to_le16(0x301) /* byte-addressable non-energy backed */



enum {

	NFIT_BLK_READ_FLUSH = 1,