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Commit 1b9f0d24 authored by Andre Przywara's avatar Andre Przywara Committed by Greg Kroah-Hartman
Browse files

arm64: dts: freescale: Fix SP805 clock-names 



[ Upstream commit f2dc2359b75e1fd345fd710862f73db20dc55864 ]

The SP805 binding sets the order of the clock-names to be: "wdog_clk",
"apb_pclk" (in exactly that order).

Change the order in the DTs for Freescale platforms to match that. The
two clocks given in all nodes are actually the same, so that does not
change any behaviour.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 27e53e23

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -496,14 +496,14 @@ 
			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;

			clocks = <&clockgen 4 15>, <&clockgen 4 15>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster1_core1_watchdog: watchdog@c010000 {

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc010000 0x0 0x1000>;

			clocks = <&clockgen 4 15>, <&clockgen 4 15>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		sai1: audio-controller@f100000 {

arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -640,56 +640,56 @@ 
			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster1_core1_watchdog: wdt@c010000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc010000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster1_core2_watchdog: wdt@c020000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc020000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster1_core3_watchdog: wdt@c030000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc030000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core0_watchdog: wdt@c100000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc100000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core1_watchdog: wdt@c110000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc110000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core2_watchdog: wdt@c120000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc120000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core3_watchdog: wdt@c130000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc130000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		fsl_mc: fsl-mc@80c000000 {

arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -230,56 +230,56 @@ 
			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster1_core1_watchdog: wdt@c010000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc010000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core0_watchdog: wdt@c100000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc100000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core1_watchdog: wdt@c110000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc110000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster3_core0_watchdog: wdt@c200000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc200000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster3_core1_watchdog: wdt@c210000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc210000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster4_core0_watchdog: wdt@c300000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc300000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster4_core1_watchdog: wdt@c310000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc310000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

			clock-names = "wdog_clk", "apb_pclk";

		};



		crypto: crypto@8000000 {