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Commit 1b8714f7 authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville
Browse files

ath9k_hw: clean up hardware revision checks 



- AR_SREV_5416_20_OR_LATER is always true, remove it
- AR_SREV_9280_20_OR_LATER is always true within eeprom_4k.c and eeprom_9287.c
- (AR_SREV_9271 || AR_SREV_9285) is always true in eeprom_4k.c

Signed-off-by: default avatarFelix Fietkau <nbd@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent f11cc949

drivers/net/wireless/ath/ath9k/ar5008_phy.c

+1 −2
Original line number Diff line number Diff line
@@ -704,8 +704,7 @@ static void ar5008_hw_override_ini(struct ath_hw *ah, 
		REG_WRITE(ah, AR_PCU_MISC_MODE2, val);

	}



	if (!AR_SREV_5416_20_OR_LATER(ah) ||

	    AR_SREV_9280_20_OR_LATER(ah))

	if (AR_SREV_9280_20_OR_LATER(ah))

		return;

	/*

	 * Disable BB clock gating

drivers/net/wireless/ath/ath9k/eeprom.c

+1 −6
Original line number Diff line number Diff line
@@ -456,12 +456,7 @@ void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, 
		pPdGainBoundaries[i] =

			min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);



		if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {

			minDelta = pPdGainBoundaries[0] - 23;

			pPdGainBoundaries[0] = 23;

		} else {

		minDelta = 0;

		}



		if (i == 0) {

			if (AR_SREV_9280_20_OR_LATER(ah))

drivers/net/wireless/ath/ath9k/eeprom_4k.c

+38 −47
Original line number Diff line number Diff line
@@ -405,11 +405,6 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 
	REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);



	for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {

		if (AR_SREV_5416_20_OR_LATER(ah) &&

		    (ah->rxchainmask == 5 || ah->txchainmask == 5) &&

		    (i != 0)) {

			regChainOffset = (i == 1) ? 0x2000 : 0x1000;

		} else

		regChainOffset = i * 0x1000;



		if (pEepData->baseEepHeader.txMask & (1 << i)) {
@@ -423,7 +418,6 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 


			ENABLE_REGWRITE_BUFFER(ah);



			if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {

			REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,

				  SM(pdGainOverlap_t2,

				     AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
@@ -435,7 +429,6 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 
				       AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)

				  | SM(gainBoundaries[3],

			       AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));

			}



			regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;

			for (j = 0; j < 32; j++) {
@@ -715,10 +708,8 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, 
	if (test)

	    return;



	if (AR_SREV_9280_20_OR_LATER(ah)) {

	for (i = 0; i < Ar5416RateSize; i++)

		ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;

	}



	ENABLE_REGWRITE_BUFFER(ah);
@@ -877,6 +868,7 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, 
	u8 txRxAttenLocal;

	u8 ob[5], db1[5], db2[5];

	u8 ant_div_control1, ant_div_control2;

	u8 bb_desired_scale;

	u32 regVal;



	pModal = &eep->modalHeader;
@@ -1096,8 +1088,8 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, 
				      AR_PHY_SETTLING_SWITCH,

				      pModal->swSettleHt40);

	}

	if (AR_SREV_9271(ah) || AR_SREV_9285(ah)) {

		u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &



	bb_desired_scale = (pModal->bb_scale_smrt_antenna &

			EEP_4K_BB_DESIRED_SCALE_MASK);

	if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {

		u32 pwrctrl, mask, clr;
@@ -1121,7 +1113,6 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, 
		REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);

	}

}

}



static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)

{

drivers/net/wireless/ath/ath9k/eeprom_9287.c

+2 −4
Original line number Diff line number Diff line
@@ -851,10 +851,8 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, 
	if (test)

		return;



	if (AR_SREV_9280_20_OR_LATER(ah)) {

	for (i = 0; i < Ar5416RateSize; i++)

		ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;

	}



	ENABLE_REGWRITE_BUFFER(ah);

drivers/net/wireless/ath/ath9k/eeprom_def.c

+20 −26
Original line number Diff line number Diff line
@@ -547,8 +547,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah, 
				break;

		}



		if (AR_SREV_5416_20_OR_LATER(ah) &&

		    (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))

		if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))

			regChainOffset = (i == 1) ? 0x2000 : 0x1000;

		else

			regChainOffset = i * 0x1000;
@@ -565,7 +564,6 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah, 
			  SM(pModal->iqCalQCh[i],

			     AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));



		if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))

		ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,

				      regChainOffset, i);

	}
@@ -893,8 +891,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, 
		      xpdGainValues[2]);



	for (i = 0; i < AR5416_MAX_CHAINS; i++) {

		if (AR_SREV_5416_20_OR_LATER(ah) &&

		    (ah->rxchainmask == 5 || ah->txchainmask == 5) &&

		if ((ah->rxchainmask == 5 || ah->txchainmask == 5) &&

		    (i != 0)) {

			regChainOffset = (i == 1) ? 0x2000 : 0x1000;

		} else
@@ -935,7 +932,6 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, 


			ENABLE_REGWRITE_BUFFER(ah);



			if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {

			if (OLC_FOR_AR9280_20_LATER) {

				REG_WRITE(ah,

					AR_PHY_TPCRG5 + regChainOffset,
@@ -953,8 +949,6 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, 
					SM_PDGAIN_B(2, 3) |

					SM_PDGAIN_B(3, 4));

			}

			}





			ath9k_adjust_pdadc_values(ah, pwr_table_offset,

						  diff, pdadcValues);