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Commit 1b866d34 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add MX entries for PCIe on sdxlemur 

To properly support PCIe Gen4 on sdxlemur, PCIe needs to vote
and scale MX rails accordingly. Add the required MX entries to
enable PCIe bus driver to do so for sdxlemur.

Change-Id: Ia56142013d07c9a811f5357e8ce29fdb3c76dd39
parent 209cc5d1

qcom/sdxlemur-pcie.dtsi

+20 −5
Original line number Diff line number Diff line
@@ -46,15 +46,30 @@ 
		vreg-1p8-supply = <&pmx65_l1>;

		vreg-0p9-supply = <&pmx65_l4>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;

		vreg-mx-supply = <&VDD_MXA_LEVEL>;



		qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>;

		qcom,vreg-0p9-voltage-level = <912000 912000 132000>;

		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;

		qcom,bw-scale =

			<RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen1 */

			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen2 */

			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen3 */

			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; /* Gen4 */

		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;

		qcom,bw-scale = /* Gen1 */

				<RPMH_REGULATOR_LEVEL_LOW_SVS

				RPMH_REGULATOR_LEVEL_LOW_SVS

				100000000

				/* Gen2 */

				RPMH_REGULATOR_LEVEL_LOW_SVS

				RPMH_REGULATOR_LEVEL_LOW_SVS

				100000000

				/* Gen3 */

				RPMH_REGULATOR_LEVEL_LOW_SVS

				RPMH_REGULATOR_LEVEL_LOW_SVS

				100000000

				/* Gen4 */

				RPMH_REGULATOR_LEVEL_LOW_SVS

				RPMH_REGULATOR_LEVEL_NOM

				100000000>;



		interconnect-names = "icc_path";

		interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;