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Commit 1b4d7d75 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: fix internal tmds setup on legacy display engine 



- crtc 0 routing was wrong
- need to clear various timing bits in FP_GEN_CNTL
- need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 8c2a6d73

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

+3 −0
Original line number Diff line number Diff line
@@ -668,6 +668,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod 


		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);

		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);



		WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);

		WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);

	} else {

		uint32_t crtc_gen_cntl;

		uint32_t crtc_ext_cntl;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

+9 −1
Original line number Diff line number Diff line
@@ -542,6 +542,14 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, 


    fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);



    fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |

		     RADEON_FP_DFP_SYNC_SEL |

		     RADEON_FP_CRT_SYNC_SEL |

		     RADEON_FP_CRTC_LOCK_8DOT |

		     RADEON_FP_USE_SHADOW_EN |

		     RADEON_FP_CRTC_USE_SHADOW_VEND |

		     RADEON_FP_CRT_SYNC_ALT);



    if (1) /*  FIXME rgbBits == 8 */

	    fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */

    else
@@ -555,7 +563,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, 
		    else

			    fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;

	    } else

		    fp_gen_cntl |= RADEON_FP_SEL_CRTC1;

		    fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;

    } else {

	    if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {

		    fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;