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Commit 1ae73f2f authored by Ben Skeggs's avatar Ben Skeggs
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drm/nvc0/pm: restrict pll mode to clocks that can actually use it 



Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 44ab8cc5

drivers/gpu/drm/nouveau/nvc0_pm.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -269,7 +269,7 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq) 
	clk0 = calc_div(dev, clk, clk0, freq, &div1D);

	clk0 = calc_div(dev, clk, clk0, freq, &div1D);





	/* see if we can get any closer using PLLs */

	/* see if we can get any closer using PLLs */

	if (clk0 != freq) {

	if (clk0 != freq && (0x00004387 & (1 << clk))) {

		if (clk < 7)

		if (clk < 7)

			clk1 = calc_pll(dev, clk, freq, &info->coef);

			clk1 = calc_pll(dev, clk, freq, &info->coef);

		else

		else