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Commit 1acc6bde authored by Kieran Bingham's avatar Kieran Bingham Committed by Archit Taneja
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drm: bridge: dw-hdmi: Remove PHY configuration resolution parameter 



The current code hard codes the call of hdmi_phy_configure() to be 8bpp
and provides extraneous error checking to verify that this hardcoded
value is correct. Simplify the implementation by removing the argument.

Signed-off-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: default avatarJose Abreu <joabreu@synopsys.com>
Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-12-laurent.pinchart+renesas@ideasonboard.com
parent 69497eb9

drivers/gpu/drm/bridge/dw-hdmi.c

+5 −22
Original line number Diff line number Diff line
@@ -930,31 +930,14 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 
			 HDMI_PHY_CONF0_SELDIPIF_MASK);

}



static int hdmi_phy_configure(struct dw_hdmi *hdmi,

			      unsigned char res, int cscon)

static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon)

{

	unsigned res_idx;

	u8 val, msec;

	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;

	const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;

	const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;

	const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;



	switch (res) {

	case 0:	/* color resolution 0 is 8 bit colour depth */

	case 8:

		res_idx = DW_HDMI_RES_8;

		break;

	case 10:

		res_idx = DW_HDMI_RES_10;

		break;

	case 12:

		res_idx = DW_HDMI_RES_12;

		break;

	default:

		return -EINVAL;

	}



	/* PLL/MPLL Cfg - always match on final entry */

	for (; mpll_config->mpixelclock != ~0UL; mpll_config++)

		if (hdmi->hdmi_data.video_mode.mpixelclock <=
@@ -1004,11 +987,11 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, 
		    HDMI_PHY_I2CM_SLAVE_ADDR);

	hdmi_phy_test_clear(hdmi, 0);



	hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);

	hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);

	hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 0x06);

	hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 0x15);



	/* CURRCTRL */

	hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);

	hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 0x10);



	hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */

	hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
@@ -1068,7 +1051,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) 
		dw_hdmi_phy_enable_powerdown(hdmi, true);



		/* Enable CSC */

		ret = hdmi_phy_configure(hdmi, 8, cscon);

		ret = hdmi_phy_configure(hdmi, cscon);

		if (ret)

			return ret;

	}