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Commit 1ac40121 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "interconnect: qcom: Add OSM L3 support on SCSHRIKE"

parents 629b150b 3dde3cb4

drivers/interconnect/qcom/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -26,6 +26,18 @@ config INTERCONNECT_QCOM_QCS404 
	  This is a driver for the Qualcomm Network-on-Chip on qcs404-based

	  platforms.



config INTERCONNECT_QCOM_SCSHRIKE

	tristate "SCSHRIKE interconnect driver"

	depends on INTERCONNECT_QCOM

	depends on QCOM_RPMH && QCOM_COMMAND_DB && OF

	select INTERCONNECT_QCOM_BCM_VOTER

	select INTERCONNECT_QCOM_RPMH

	help

	  This is a driver for the Qualcomm Technologies, Inc. Network-on-Chip

	  on scshrike-based platforms. The interconnect provider collects and

	  aggreagates the cosumer bandwidth requests to satisfy constraints

	  placed on Network-on-Chip performance states.



config INTERCONNECT_QCOM_SDM845

	tristate "Qualcomm SDM845 interconnect driver"

	depends on INTERCONNECT_QCOM

drivers/interconnect/qcom/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 


qnoc-holi-objs			:= holi.o

qnoc-qcs404-objs			:= qcs404.o

qnoc-scshrike-objs			:= scshrike.o

qnoc-sdm845-objs			:= sdm845.o

qnoc-lahaina-objs			:= lahaina.o

qnoc-sdxlemur-objs			:= sdxlemur.o
@@ -18,6 +19,7 @@ qnoc-qos-obj := qnoc-qos.o 
obj-$(CONFIG_INTERCONNECT_QCOM_HOLI) += qnoc-holi.o

obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += osm-l3.o

obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o

obj-$(CONFIG_INTERCONNECT_QCOM_SCSHRIKE) += qnoc-scshrike.o

obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o

obj-$(CONFIG_INTERCONNECT_QCOM_LAHAINA) += qnoc-lahaina.o

drivers/interconnect/qcom/osm-l3.c

+35 −17
Original line number Diff line number Diff line
@@ -90,25 +90,22 @@ const static struct qcom_icc_desc sdm845_icc_osm_l3 = { 
	.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),

};



DEFINE_QNODE(sm8150_osm_apps_l3, OSM_MASTER_L3_APPS, 1,

		OSM_SLAVE_L3, OSM_SLAVE_L3_CLUSTER0,

		OSM_SLAVE_L3_CLUSTER1, OSM_SLAVE_L3_CLUSTER2,

		OSM_SLAVE_L3_MISC, OSM_SLAVE_L3_GPU);

DEFINE_QNODE(sm8150_osm_l3, OSM_SLAVE_L3, 1);

DEFINE_QNODE(sm8150_osm_l3_cluster0, OSM_SLAVE_L3_CLUSTER0, 1);

DEFINE_QNODE(sm8150_osm_l3_cluster1, OSM_SLAVE_L3_CLUSTER1, 1);

DEFINE_QNODE(sm8150_osm_l3_cluster2, OSM_SLAVE_L3_CLUSTER2, 1);

DEFINE_QNODE(sm8150_osm_l3_misc, OSM_SLAVE_L3_MISC, 1);

DEFINE_QNODE(sm8150_osm_l3_gpu, OSM_SLAVE_L3_GPU, 1);

DEFINE_QNODE(mas_osm_l3_apps, OSM_MASTER_L3_APPS, 1,

		OSM_SLAVE_L3_CLUSTER0, OSM_SLAVE_L3_CLUSTER1,

		OSM_SLAVE_L3_CLUSTER2, OSM_SLAVE_L3_MISC, OSM_SLAVE_L3_GPU);

DEFINE_QNODE(slv_osm_l3_cluster0, OSM_SLAVE_L3_CLUSTER0, 1);

DEFINE_QNODE(slv_osm_l3_cluster1, OSM_SLAVE_L3_CLUSTER1, 1);

DEFINE_QNODE(slv_osm_l3_cluster2, OSM_SLAVE_L3_CLUSTER2, 1);

DEFINE_QNODE(slv_osm_l3_misc, OSM_SLAVE_L3_MISC, 1);

DEFINE_QNODE(slv_osm_l3_gpu, OSM_SLAVE_L3_GPU, 1);



static struct qcom_icc_node *sm8150_osm_l3_nodes[] = {

	[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,

	[SLAVE_OSM_L3] = &sm8150_osm_l3,

	[SLAVE_OSM_L3_CLUSTER0] = &sm8150_osm_l3_cluster0,

	[SLAVE_OSM_L3_CLUSTER1] = &sm8150_osm_l3_cluster1,

	[SLAVE_OSM_L3_CLUSTER2] = &sm8150_osm_l3_cluster2,

	[SLAVE_OSM_L3_MISC] = &sm8150_osm_l3_misc,

	[SLAVE_OSM_L3_GPU] = &sm8150_osm_l3_gpu,

	[MASTER_OSM_L3_APPS] = &mas_osm_l3_apps,

	[SLAVE_OSM_L3_CLUSTER0] = &slv_osm_l3_cluster0,

	[SLAVE_OSM_L3_CLUSTER1] = &slv_osm_l3_cluster1,

	[SLAVE_OSM_L3_CLUSTER2] = &slv_osm_l3_cluster2,

	[SLAVE_OSM_L3_MISC] = &slv_osm_l3_misc,

	[SLAVE_OSM_L3_GPU] = &slv_osm_l3_gpu,

};



static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
@@ -116,6 +113,23 @@ static const struct qcom_icc_desc sm8150_icc_osm_l3 = { 
	.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),

};





DEFINE_QNODE(mas_osm_l3_apps_scshrike, OSM_MASTER_L3_APPS, 1,

		OSM_SLAVE_L3_CLUSTER0, OSM_SLAVE_L3_CLUSTER1,

		OSM_SLAVE_L3_MISC, OSM_SLAVE_L3_GPU);



static struct qcom_icc_node *scshrike_osm_l3_nodes[] = {

	[MASTER_OSM_L3_APPS] = &mas_osm_l3_apps_scshrike,

	[SLAVE_OSM_L3_CLUSTER0] = &slv_osm_l3_cluster0,

	[SLAVE_OSM_L3_CLUSTER1] = &slv_osm_l3_cluster1,

	[SLAVE_OSM_L3_MISC] = &slv_osm_l3_misc,

	[SLAVE_OSM_L3_GPU] = &slv_osm_l3_gpu,

};



static const struct qcom_icc_desc scshrike_icc_osm_l3 = {

	.nodes = scshrike_osm_l3_nodes,

	.num_nodes = ARRAY_SIZE(scshrike_osm_l3_nodes),

};

static int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,

		u32 peak_bw, u32 *agg_avg, u32 *agg_peak)

{
@@ -256,6 +270,9 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) 
	for (i = 0; i < num_nodes; i++) {

		size_t j;



		if (!qnodes[i])

			continue;



		node = icc_node_create(qnodes[i]->id);

		if (IS_ERR(node)) {

			ret = PTR_ERR(node);
@@ -285,6 +302,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) 
static const struct of_device_id osm_l3_of_match[] = {

	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },

	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },

	{ .compatible = "qcom,scshrike-osm-l3", .data = &scshrike_icc_osm_l3 },

	{ }

};

MODULE_DEVICE_TABLE(of, osm_l3_of_match);