Merge "cnss2: Add SRAM mem dump for debug" (1abff4a1) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/net/wireless/cnss2/pci.c

+17 −0

Original line number	Original line	Diff line number	Diff line
	@@ -74,6 +74,9 @@ static DEFINE_SPINLOCK(time_sync_lock);

	#define LINK_TRAINING_RETRY_MAX_TIMES 3		#define LINK_TRAINING_RETRY_MAX_TIMES 3

			#define CNSS_DEBUG_DUMP_SRAM_START 0x1403D58
			#define CNSS_DEBUG_DUMP_SRAM_SIZE 10

	static struct cnss_pci_reg ce_src[] = {		static struct cnss_pci_reg ce_src[] = {
	{ "SRC_RING_BASE_LSB", QCA6390_CE_SRC_RING_BASE_LSB_OFFSET },		{ "SRC_RING_BASE_LSB", QCA6390_CE_SRC_RING_BASE_LSB_OFFSET },
	{ "SRC_RING_BASE_MSB", QCA6390_CE_SRC_RING_BASE_MSB_OFFSET },		{ "SRC_RING_BASE_MSB", QCA6390_CE_SRC_RING_BASE_MSB_OFFSET },
	@@ -3734,6 +3737,19 @@ static void cnss_pci_dump_ce_reg(struct cnss_pci_data *pci_priv,
	}		}
	}		}

			static void cnss_pci_dump_sram_mem(struct cnss_pci_data *pci_priv)
			{
			int i;
			u32 mem_addr, val;

			for (i = 0; i < CNSS_DEBUG_DUMP_SRAM_SIZE; i++) {
			mem_addr = CNSS_DEBUG_DUMP_SRAM_START + i * 4;
			if (cnss_pci_reg_read(pci_priv, mem_addr, &val))
			return;
			cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);
			}
			}

	static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv)		static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv)
	{		{
	cnss_pr_dbg("Start to dump debug registers\n");		cnss_pr_dbg("Start to dump debug registers\n");
	@@ -3742,6 +3758,7 @@ static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv)
	return;		return;

	mhi_debug_reg_dump(pci_priv->mhi_ctrl);		mhi_debug_reg_dump(pci_priv->mhi_ctrl);
			cnss_pci_dump_sram_mem(pci_priv);
	cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON);		cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON);
	cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09);		cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09);
	cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10);		cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10);