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Commit 1a4e6203 authored by Robin Murphy's avatar Robin Murphy Committed by Heiko Stuebner
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arm64: dts: rockchip: Add nanopi4 ethernet phy 



The nanopi4 boards have the INTB pin of the RTL8211E phy wired up, so we
can make use of that and avoid having to poll for line status changes.
Apparently RTL8211E only requires 30ms of post-reset delay, so we may as
well save a little bit of time there as well.

Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 980b5216

arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi

+25 −2
Original line number Diff line number Diff line
@@ -148,15 +148,28 @@ 
	assigned-clocks = <&cru SCLK_RMII_SRC>;

	clock_in_out = "input";

	pinctrl-names = "default";

	pinctrl-0 = <&rgmii_pins>;

	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;

	phy-handle = <&rtl8211e>;

	phy-mode = "rgmii";

	phy-supply = <&vcc3v3_s3>;

	snps,reset-active-low;

	snps,reset-delays-us = <0 10000 50000>;

	snps,reset-delays-us = <0 10000 30000>;

	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;

	tx_delay = <0x28>;

	rx_delay = <0x11>;

	status = "okay";



	mdio {

		compatible = "snps,dwmac-mdio";

		#address-cells = <1>;

		#size-cells = <0>;



		rtl8211e: phy@1 {

			reg = <1>;

			interrupt-parent = <&gpio3>;

			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;

		};

	};

};



&gpu {
@@ -481,6 +494,16 @@ 
		};

	};



	phy {

		phy_intb: phy-intb {

			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;

		};



		phy_rstb: phy-rstb {

			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};



	pmic {

		cpu_b_sleep: cpu-b-sleep {

			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;