Commit 1a1ebd5f authored Feb 04, 2016 by Tirumalesh Chalamarla Committed by Marc Zyngier Feb 11, 2016

irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor



The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:

	4.1.1 Physical CPU Interface:
	The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
	on the state of a returned INTID are not guaranteed
	to be visible until after the execution of a DSB.

Not having this could result in missed interrupts, so let's add the
required barrier.

[Marc: fixed commit message]

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

parent 389a00d3

arch/arm64/include/asm/arch_gicv3.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
	u64 irqstat;		u64 irqstat;

	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));		asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
			dsb(sy);
	return irqstat;		return irqstat;
	}		}