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Commit 19df9a57 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala
Browse files

drm/i915: Move execlist initialization into intel_engine_cs.c 



Move execlist init into a common engine setup. As it is
common to both guc and hw execlists.

v2: rebase with csb changes
v3: rebase

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170922124307.10914-2-mika.kuoppala@intel.com
parent b620e870

drivers/gpu/drm/i915/intel_engine_cs.c

+28 −2
Original line number Diff line number Diff line
@@ -382,6 +382,33 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine) 
	engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];

}



static bool csb_force_mmio(struct drm_i915_private *i915)

{

	/* GVT emulation depends upon intercepting CSB mmio */

	if (intel_vgpu_active(i915))

		return true;



	/*

	 * IOMMU adds unpredictable latency causing the CSB write (from the

	 * GPU into the HWSP) to only be visible some time after the interrupt

	 * (missed breadcrumb syndrome).

	 */

	if (intel_vtd_active())

		return true;



	return false;

}



static void intel_engine_init_execlist(struct intel_engine_cs *engine)

{

	struct intel_engine_execlists * const execlists = &engine->execlists;



	execlists->csb_use_mmio = csb_force_mmio(engine->i915);



	execlists->queue = RB_ROOT;

	execlists->first = NULL;

}



/**

 * intel_engines_setup_common - setup engine state not requiring hw access

 * @engine: Engine to setup.
@@ -393,8 +420,7 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine) 
 */

void intel_engine_setup_common(struct intel_engine_cs *engine)

{

	engine->execlists.queue = RB_ROOT;

	engine->execlists.first = NULL;

	intel_engine_init_execlist(engine);



	intel_engine_init_timeline(engine);

	intel_engine_init_hangcheck(engine);

drivers/gpu/drm/i915/intel_lrc.c

+0 −19
Original line number Diff line number Diff line
@@ -1784,23 +1784,6 @@ logical_ring_default_irqs(struct intel_engine_cs *engine) 
	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;

}



static bool irq_handler_force_mmio(struct drm_i915_private *i915)

{

	/* GVT emulation depends upon intercepting CSB mmio */

	if (intel_vgpu_active(i915))

		return true;



	/*

	 * IOMMU adds unpredictable latency causing the CSB write (from the

	 * GPU into the HWSP) to only be visible some time after the interrupt

	 * (missed breadcrumb syndrome).

	 */

	if (intel_vtd_active())

		return true;



	return false;

}



static void

logical_ring_setup(struct intel_engine_cs *engine)

{
@@ -1812,8 +1795,6 @@ logical_ring_setup(struct intel_engine_cs *engine) 
	/* Intentionally left blank. */

	engine->buffer = NULL;



	engine->execlists.csb_use_mmio = irq_handler_force_mmio(dev_priv);



	fw_domains = intel_uncore_forcewake_for_reg(dev_priv,

						    RING_ELSP(engine),

						    FW_REG_WRITE);