Loading qcom/shima.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -1102,6 +1102,25 @@ <CONTROL_TCS 0>; }; spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, <0xc600000 0x2000000>, <0xe600000 0x100000>, <0xe700000 0xa0000>, <0xc40a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "periph_irq"; interrupt-controller; #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <0>; cell-index = <0>; qcom,channel = <0>; qcom,ee = <0>; }; qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; Loading Loading
qcom/shima.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -1102,6 +1102,25 @@ <CONTROL_TCS 0>; }; spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, <0xc600000 0x2000000>, <0xe600000 0x100000>, <0xe700000 0xa0000>, <0xc40a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "periph_irq"; interrupt-controller; #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <0>; cell-index = <0>; qcom,channel = <0>; qcom,ee = <0>; }; qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; Loading