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Commit 199ea381 authored by Maarten Lankhorst's avatar Maarten Lankhorst
Browse files

drm/i915: Pass crtc_state to ips toggle functions, v2 



Changes since v1:
- Only pass crtc_state, not crtc.

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171110113503.16253-8-maarten.lankhorst@linux.intel.com


Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent 93313538

drivers/gpu/drm/i915/intel_color.c

+2 −2
Original line number Diff line number Diff line
@@ -370,7 +370,7 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state) 
	 */

	if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&

	    (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {

		hsw_disable_ips(intel_crtc);

		hsw_disable_ips(intel_crtc_state);

		reenable_ips = true;

	}
@@ -380,7 +380,7 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state) 
	i9xx_load_luts(crtc_state);



	if (reenable_ips)

		hsw_enable_ips(intel_crtc);

		hsw_enable_ips(intel_crtc_state);

}



static void bdw_load_degamma_lut(struct drm_crtc_state *state)

drivers/gpu/drm/i915/intel_display.c

+14 −10
Original line number Diff line number Diff line
@@ -4864,8 +4864,9 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc) 
	}

}



void hsw_enable_ips(struct intel_crtc *crtc)

void hsw_enable_ips(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4903,12 +4904,13 @@ void hsw_enable_ips(struct intel_crtc *crtc) 
	}

}



void hsw_disable_ips(struct intel_crtc *crtc)

void hsw_disable_ips(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);



	if (!crtc->config->ips_enabled)

	if (!crtc_state->ips_enabled)

		return;



	assert_plane_enabled(dev_priv, crtc->plane);
@@ -4956,7 +4958,8 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) 
 * completely hide the primary plane.

 */

static void

intel_post_enable_primary(struct drm_crtc *crtc)

intel_post_enable_primary(struct drm_crtc *crtc,

			  const struct intel_crtc_state *new_crtc_state)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4969,7 +4972,7 @@ intel_post_enable_primary(struct drm_crtc *crtc) 
	 * when going from primary only to sprite only and vice

	 * versa.

	 */

	hsw_enable_ips(intel_crtc);

	hsw_enable_ips(new_crtc_state);



	/*

	 * Gen2 reports pipe underruns whenever all planes are disabled.
@@ -4988,7 +4991,8 @@ intel_post_enable_primary(struct drm_crtc *crtc) 


/* FIXME move all this to pre_plane_update() with proper state tracking */

static void

intel_pre_disable_primary(struct drm_crtc *crtc)

intel_pre_disable_primary(struct drm_crtc *crtc,

			  const struct intel_crtc_state *old_crtc_state)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -5010,7 +5014,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc) 
	 * when going from primary only to sprite only and vice

	 * versa.

	 */

	hsw_disable_ips(intel_crtc);

	hsw_disable_ips(old_crtc_state);

}



/* FIXME get rid of this and use pre_plane_update */
@@ -5022,7 +5026,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;



	intel_pre_disable_primary(crtc);

	intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state));



	/*

	 * Vblank time updates from the shadow to live plane control register
@@ -5066,7 +5070,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) 
		if (primary_state->base.visible &&

		    (needs_modeset(&pipe_config->base) ||

		     !old_primary_state->base.visible))

			intel_post_enable_primary(&crtc->base);

			intel_post_enable_primary(&crtc->base, pipe_config);

	}

}
@@ -5095,7 +5099,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, 


		if (old_primary_state->base.visible &&

		    (modeset || !primary_state->base.visible))

			intel_pre_disable_primary(&crtc->base);

			intel_pre_disable_primary(&crtc->base, old_crtc_state);

	}



	/*

drivers/gpu/drm/i915/intel_dp.c

+3 −3
Original line number Diff line number Diff line
@@ -3903,7 +3903,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp, 


 out:

	if (disable_wa)

		hsw_enable_ips(intel_crtc);

		hsw_enable_ips(crtc_state);

	return ret;

}
@@ -3931,11 +3931,11 @@ static int intel_dp_sink_crc_start(struct intel_dp *intel_dp, 
			return ret;

	}



	hsw_disable_ips(intel_crtc);

	hsw_disable_ips(crtc_state);



	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,

			       buf | DP_TEST_SINK_START) < 0) {

		hsw_enable_ips(intel_crtc);

		hsw_enable_ips(crtc_state);

		return -EIO;

	}

drivers/gpu/drm/i915/intel_drv.h

+2 −2
Original line number Diff line number Diff line
@@ -1485,8 +1485,8 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, 
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);



bool intel_crtc_active(struct intel_crtc *crtc);

void hsw_enable_ips(struct intel_crtc *crtc);

void hsw_disable_ips(struct intel_crtc *crtc);

void hsw_enable_ips(const struct intel_crtc_state *crtc_state);

void hsw_disable_ips(const struct intel_crtc_state *crtc_state);

enum intel_display_power_domain intel_port_to_power_domain(enum port port);

void intel_mode_from_pipe_config(struct drm_display_mode *mode,

				 struct intel_crtc_state *pipe_config);