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Commit 19592668 authored by Tony Truong's avatar Tony Truong
Browse files

ARM: dts: msm: add PCIe AUX CLK freq entry for PCIe0 and PCIe1 for lahaina 

Have both PCIe0 and PCIe1 explicitly program their respective
controller PCIe AUX CLK frequency setting with 19.2MHz on
lahaina.

Change-Id: If1c2508f64aa2167d93d99d0248cfbd3d8ce27b6
parent 5056f248

qcom/lahaina-pcie.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ 
			<0x100 &apps_smmu 0x1c01 0x1>;



		qcom,boot-option = <0x1>;

		qcom,aux-clk-freq = <20>; /* 19.2 MHz */

		qcom,drv-supported;

		qcom,l1ss-sleep-disable = <0x1>;

		qcom,drv-l1ss-timeout-us = <5000>;
@@ -328,6 +329,7 @@ 
			<0x100 &apps_smmu 0x1c81 0x1>;



		qcom,boot-option = <0x1>;

		qcom,aux-clk-freq = <20>; /* 19.2 MHz */

		qcom,drv-supported;

		qcom,wr-halt-size = <0x8>;

		qcom,no-l0s-supported;