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Commit 18fb053f authored by Matthew Whitehead's avatar Matthew Whitehead Committed by Thomas Gleixner
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x86/cpu/cyrix: Use correct macros for Cyrix calls on Geode processors 



There are comments in processor-cyrix.h advising you to _not_ make calls
using the deprecated macros in this style:

  setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);

This is because it expands the macro into a non-functioning calling
sequence. The calling order must be:

  outb(CX86_CCR2, 0x22);
  inb(0x23);

From the comments:

 * When using the old macros a line like
 *   setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
 * gets expanded to:
 *  do {
 *    outb((CX86_CCR2), 0x22);
 *    outb((({
 *        outb((CX86_CCR2), 0x22);
 *        inb(0x23);
 *    }) | 0x88), 0x23);
 *  } while (0);

The new macros fix this problem, so use them instead. Tested on an
actual Geode processor.

Signed-off-by: default avatarMatthew Whitehead <tedheadster@gmail.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: luto@kernel.org
Link: https://lkml.kernel.org/r/1552596361-8967-2-git-send-email-tedheadster@gmail.com
parent 9bd68125

arch/x86/kernel/cpu/cyrix.c

+7 −7
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ static void set_cx86_reorder(void) 
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */



	/* Load/Store Serialize to mem access disable (=reorder it) */

	setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);

	setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);

	/* set load/store serialize from 1GB to 4GB */

	ccr3 |= 0xe0;

	setCx86(CX86_CCR3, ccr3);
@@ -135,11 +135,11 @@ static void set_cx86_memwb(void) 
	pr_info("Enable Memory-Write-back mode on Cyrix/NSC processor.\n");



	/* CCR2 bit 2: unlock NW bit */

	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);

	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);

	/* set 'Not Write-through' */

	write_cr0(read_cr0() | X86_CR0_NW);

	/* CCR2 bit 2: lock NW bit and set WT1 */

	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);

	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);

}



/*
@@ -153,14 +153,14 @@ static void geode_configure(void) 
	local_irq_save(flags);



	/* Suspend on halt power saving and enable #SUSP pin */

	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);

	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);



	ccr3 = getCx86(CX86_CCR3);

	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */





	/* FPU fast, DTE cache, Mem bypass */

	setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);

	setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);

	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */



	set_cx86_memwb();
@@ -296,7 +296,7 @@ static void init_cyrix(struct cpuinfo_x86 *c) 
		/* GXm supports extended cpuid levels 'ala' AMD */

		if (c->cpuid_level == 2) {

			/* Enable cxMMX extensions (GX1 Datasheet 54) */

			setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);

			setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);



			/*

			 * GXm : 0x30 ... 0x5f GXm  datasheet 51
@@ -319,7 +319,7 @@ static void init_cyrix(struct cpuinfo_x86 *c) 
		if (dir1 > 7) {

			dir0_msn++;  /* M II */

			/* Enable MMX extensions (App note 108) */

			setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);

			setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);

		} else {

			/* A 6x86MX - it has the bug. */

			set_cpu_bug(c, X86_BUG_COMA);