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Commit 18845557 authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'wireless-drivers-next-for-davem-2018-03-29' of...

Merge tag 'wireless-drivers-next-for-davem-2018-03-29' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next



Kalle Valo says:

====================
wireless-drivers-next patches for 4.17

Smaller new features to various drivers but nothing really out of
ordinary.

Major changes:

ath10k

* enable chip temperature measurement for QCA6174/QCA9377

* add firmware memory dump for QCA9984

* enable buffer STA on TDLS link for QCA6174

* support different beacon internals in multiple interface scenario
  for QCA988X/QCA99X0/QCA9984/QCA4019

iwlwifi

* support for new PCI IDs for the 9000 family

* support for a new firmware API version

* support for advanced dwell and Optimized Connectivity Experience
  (OCE) in scanning

btrsi

* fix kconfig dependencies

wil6210

* support multiple virtual interfaces
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e15f20ea 14c99949
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+1 −3
Original line number Diff line number Diff line
@@ -393,9 +393,7 @@ config BT_QCOMSMD
	  kernel or say M to compile as a module.

config BT_HCIRSI
	tristate "Redpine HCI support"
	default n
	select RSI_COEX
	tristate
	help
	  Redpine BT driver.
	  This driver handles BT traffic from upper layers and pass
+0 −2
Original line number Diff line number Diff line
@@ -33,8 +33,6 @@
 */
#define	ATH_KEYMAX	        128     /* max key cache size we handle */

static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

struct ath_ani {
	bool caldone;
	unsigned int longcal_timer;
+7 −2
Original line number Diff line number Diff line
/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
@@ -2040,7 +2041,8 @@ static int ath10k_core_init_firmware_features(struct ath10k *ar)
		ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
		ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
		ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
					WMI_10_4_STAT_PEER_EXTD;
					WMI_10_4_STAT_PEER_EXTD |
					WMI_10_4_STAT_VDEV_EXTD;
		ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
		ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS;

@@ -2281,6 +2283,9 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
		if (ath10k_peer_stats_enabled(ar))
			val = WMI_10_4_PEER_STATS;

		/* Enable vdev stats by default */
		val |= WMI_10_4_VDEV_STATS;

		if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
			val |= WMI_10_4_BSS_CHANNEL_INFO_64;

@@ -2439,7 +2444,7 @@ static int ath10k_core_probe_fw(struct ath10k *ar)

	ret = ath10k_hif_power_up(ar);
	if (ret) {
		ath10k_err(ar, "could not start pci hif (%d)\n", ret);
		ath10k_err(ar, "could not power on hif bus (%d)\n", ret);
		return ret;
	}

+88 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
@@ -221,6 +222,27 @@ struct ath10k_fw_stats_vdev {
	u32 beacon_rssi_history[10];
};

struct ath10k_fw_stats_vdev_extd {
	struct list_head list;

	u32 vdev_id;
	u32 ppdu_aggr_cnt;
	u32 ppdu_noack;
	u32 mpdu_queued;
	u32 ppdu_nonaggr_cnt;
	u32 mpdu_sw_requeued;
	u32 mpdu_suc_retry;
	u32 mpdu_suc_multitry;
	u32 mpdu_fail_retry;
	u32 tx_ftm_suc;
	u32 tx_ftm_suc_retry;
	u32 tx_ftm_fail;
	u32 rx_ftmr_cnt;
	u32 rx_ftmr_dup_cnt;
	u32 rx_iftmr_cnt;
	u32 rx_iftmr_dup_cnt;
};

struct ath10k_fw_stats_pdev {
	struct list_head list;

@@ -324,6 +346,27 @@ struct ath10k_tpc_stats {
	struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
};

struct ath10k_tpc_table_final {
	u32 pream_idx[WMI_TPC_FINAL_RATE_MAX];
	u8 rate_code[WMI_TPC_FINAL_RATE_MAX];
	char tpc_value[WMI_TPC_FINAL_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
};

struct ath10k_tpc_stats_final {
	u32 reg_domain;
	u32 chan_freq;
	u32 phy_mode;
	u32 twice_antenna_reduction;
	u32 twice_max_rd_power;
	s32 twice_antenna_gain;
	u32 power_limit;
	u32 num_tx_chain;
	u32 ctl;
	u32 rate_max;
	u8 flag[WMI_TPC_FLAG];
	struct ath10k_tpc_table_final tpc_table_final[WMI_TPC_FLAG];
};

struct ath10k_dfs_stats {
	u32 phy_errors;
	u32 pulses_total;
@@ -354,6 +397,45 @@ struct ath10k_txq {
	unsigned long num_push_allowed;
};

enum ath10k_pkt_rx_err {
	ATH10K_PKT_RX_ERR_FCS,
	ATH10K_PKT_RX_ERR_TKIP,
	ATH10K_PKT_RX_ERR_CRYPT,
	ATH10K_PKT_RX_ERR_PEER_IDX_INVAL,
	ATH10K_PKT_RX_ERR_MAX,
};

enum ath10k_ampdu_subfrm_num {
	ATH10K_AMPDU_SUBFRM_NUM_10,
	ATH10K_AMPDU_SUBFRM_NUM_20,
	ATH10K_AMPDU_SUBFRM_NUM_30,
	ATH10K_AMPDU_SUBFRM_NUM_40,
	ATH10K_AMPDU_SUBFRM_NUM_50,
	ATH10K_AMPDU_SUBFRM_NUM_60,
	ATH10K_AMPDU_SUBFRM_NUM_MORE,
	ATH10K_AMPDU_SUBFRM_NUM_MAX,
};

enum ath10k_amsdu_subfrm_num {
	ATH10K_AMSDU_SUBFRM_NUM_1,
	ATH10K_AMSDU_SUBFRM_NUM_2,
	ATH10K_AMSDU_SUBFRM_NUM_3,
	ATH10K_AMSDU_SUBFRM_NUM_4,
	ATH10K_AMSDU_SUBFRM_NUM_MORE,
	ATH10K_AMSDU_SUBFRM_NUM_MAX,
};

struct ath10k_sta_tid_stats {
	unsigned long int rx_pkt_from_fw;
	unsigned long int rx_pkt_unchained;
	unsigned long int rx_pkt_drop_chained;
	unsigned long int rx_pkt_drop_filter;
	unsigned long int rx_pkt_err[ATH10K_PKT_RX_ERR_MAX];
	unsigned long int rx_pkt_queued_for_mac;
	unsigned long int rx_pkt_ampdu[ATH10K_AMPDU_SUBFRM_NUM_MAX];
	unsigned long int rx_pkt_amsdu[ATH10K_AMSDU_SUBFRM_NUM_MAX];
};

struct ath10k_sta {
	struct ath10k_vif *arvif;

@@ -371,6 +453,9 @@ struct ath10k_sta {
#ifdef CONFIG_MAC80211_DEBUGFS
	/* protected by conf_mutex */
	bool aggr_mode;

	/* Protected with ar->data_lock */
	struct ath10k_sta_tid_stats tid_stats[IEEE80211_NUM_TIDS + 1];
#endif
};

@@ -487,6 +572,7 @@ struct ath10k_debug {

	/* used for tpc-dump storage, protected by data-lock */
	struct ath10k_tpc_stats *tpc_stats;
	struct ath10k_tpc_stats_final *tpc_stats_final;

	struct completion tpc_complete;

@@ -1019,6 +1105,8 @@ struct ath10k {

	void *ce_priv;

	u32 sta_tid_stats_mask;

	/* must be last */
	u8 drv_priv[0] __aligned(sizeof(void *));
};
+90 −0
Original line number Diff line number Diff line
@@ -701,6 +701,89 @@ static const struct ath10k_mem_region qca988x_hw20_mem_regions[] = {
	},
};

static const struct ath10k_mem_region qca9984_hw10_mem_regions[] = {
	{
		.type = ATH10K_MEM_REGION_TYPE_DRAM,
		.start = 0x400000,
		.len = 0x80000,
		.name = "DRAM",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
	{
		.type = ATH10K_MEM_REGION_TYPE_REG,
		.start = 0x98000,
		.len = 0x50000,
		.name = "IRAM",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
	{
		.type = ATH10K_MEM_REGION_TYPE_IOSRAM,
		.start = 0xC0000,
		.len = 0x40000,
		.name = "SRAM",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
	{
		.type = ATH10K_MEM_REGION_TYPE_IOREG,
		.start = 0x30000,
		.len = 0x7000,
		.name = "APB REG 1",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
	{
		.type = ATH10K_MEM_REGION_TYPE_IOREG,
		.start = 0x3f000,
		.len = 0x3000,
		.name = "APB REG 2",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
	{
		.type = ATH10K_MEM_REGION_TYPE_IOREG,
		.start = 0x43000,
		.len = 0x3000,
		.name = "WIFI REG",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
	{
		.type = ATH10K_MEM_REGION_TYPE_IOREG,
		.start = 0x4A000,
		.len = 0x5000,
		.name = "CE REG",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
	{
		.type = ATH10K_MEM_REGION_TYPE_IOREG,
		.start = 0x80000,
		.len = 0x6000,
		.name = "SOC REG",
		.section_table = {
			.sections = NULL,
			.size = 0,
		},
	},
};

static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
	{
		.hw_id = QCA6174_HW_1_0_VERSION,
@@ -758,6 +841,13 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
			.size = ARRAY_SIZE(qca988x_hw20_mem_regions),
		},
	},
	{
		.hw_id = QCA9984_HW_1_0_DEV_VERSION,
		.region_table = {
			.regions = qca9984_hw10_mem_regions,
			.size = ARRAY_SIZE(qca9984_hw10_mem_regions),
		},
	},
};

static u32 ath10k_coredump_get_ramdump_size(struct ath10k *ar)
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