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Commit 1830a5f9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add GPU power levels for Lahaina r2"

parents 6fa6e005 b978901b

qcom/lahaina-v2-gpu.dtsi

+94 −0
Original line number Diff line number Diff line 
&msm_gpu {

	qcom,chipid = <0x06060001>;



	qcom,initial-pwrlevel = <5>;



	/* Power levels */

	qcom,gpu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;



		compatible = "qcom,gpu-pwrlevels";



		qcom,gpu-pwrlevel@0 {

			reg = <0>;

			qcom,gpu-freq = <738000000>;

			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



			qcom,bus-freq-ddr7 = <11>;

			qcom,bus-min-ddr7 = <11>;

			qcom,bus-max-ddr7 = <11>;



			qcom,bus-freq-ddr8 = <11>;

			qcom,bus-min-ddr8 = <11>;

			qcom,bus-max-ddr8 = <11>;

		};



		qcom,gpu-pwrlevel@1 {

			reg = <1>;

			qcom,gpu-freq = <676000000>;

			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;



			qcom,bus-freq-ddr7 = <11>;

			qcom,bus-min-ddr7 = <11>;

			qcom,bus-max-ddr7 = <11>;



			qcom,bus-freq-ddr8 = <10>;

			qcom,bus-min-ddr8 = <10>;

			qcom,bus-max-ddr8 = <11>;

		};



		qcom,gpu-pwrlevel@2 {

			reg = <2>;

			qcom,gpu-freq = <608000000>;

			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;



			qcom,bus-freq-ddr7 = <8>;

			qcom,bus-min-ddr7 = <7>;

			qcom,bus-max-ddr7 = <11>;



			qcom,bus-freq-ddr8 = <7>;

			qcom,bus-min-ddr8 = <7>;

			qcom,bus-max-ddr8 = <11>;

		};



		qcom,gpu-pwrlevel@3 {

			reg = <3>;

			qcom,gpu-freq = <540000000>;

			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



			qcom,bus-freq-ddr7 = <8>;

			qcom,bus-min-ddr7 = <7>;

			qcom,bus-max-ddr7 = <10>;



			qcom,bus-freq-ddr8 = <7>;

			qcom,bus-min-ddr8 = <7>;

			qcom,bus-max-ddr8 = <9>;

		};



		qcom,gpu-pwrlevel@4 {

			reg = <4>;

			qcom,gpu-freq = <443000000>;

			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



			qcom,bus-freq-ddr7 = <8>;

			qcom,bus-min-ddr7 = <6>;

			qcom,bus-max-ddr7 = <10>;



			qcom,bus-freq-ddr8 = <7>;

			qcom,bus-min-ddr8 = <6>;

			qcom,bus-max-ddr8 = <9>;

		};



		qcom,gpu-pwrlevel@5 {

			reg = <5>;

			qcom,gpu-freq = <315000000>;

			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



			qcom,bus-freq-ddr7 = <3>;

			qcom,bus-min-ddr7 = <3>;

			qcom,bus-max-ddr7 = <9>;



			qcom,bus-freq-ddr8 = <3>;

			qcom,bus-min-ddr8 = <3>;

			qcom,bus-max-ddr8 = <8>;

		};

	};

};