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Commit 17cf51a9 authored by Saurabh Sahu's avatar Saurabh Sahu
Browse files

ARM: dts: msm: Add dummy clock nodes for MONACO 

Dummy clock nodes are required for clocks client to
request, so add support for the same. Also add the
dummy GDSCs required by clients for monaco.

Change-Id: I16e204fb2c04cbe750db25af4364a8af0b252404
parent 2a1406de

qcom/monaco-gdsc.dtsi

0 → 100644
+91 −0
Original line number Diff line number Diff line 
&soc {

	/* GDSCs in GCC */

	gcc_camss_top_gdsc: qcom,gdsc@1458004 {

		compatible = "regulator-fixed";

		reg = <0x1458004 0x4>;

		regulator-name = "gcc_camss_top_gdsc";

		status = "disabled";

	};



	gcc_usb20_prim_gdsc: qcom,gdsc@141c004 {

		compatible = "regulator-fixed";

		reg = <0x141c004 0x4>;

		regulator-name = "gcc_usb20_prim_gdsc";

		status = "disabled";

	};



	gcc_vcodec0_gdsc: qcom,gdsc@14580a8 {

		compatible = "regulator-fixed";

		reg = <0x14580a8 0x4>;

		regulator-name = "gcc_vcodec0_gdsc";

		status = "disabled";

	};



	gcc_venus_gdsc: qcom,gdsc@1458084 {

		compatible = "regulator-fixed";

		reg = <0x1458084 0x4>;

		regulator-name = "gcc_venus_gdsc";

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {

		compatible = "regulator-fixed";

		reg = <0x147d078 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {

		compatible = "regulator-fixed";

		reg = <0x147d074 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	/* GDSCs in DISPCC */

	mdss_core_gdsc: qcom,gdsc@5f03000 {

		compatible = "regulator-fixed";

		reg = <0x5f03000 0x4>;

		regulator-name = "mdss_core_gdsc";

		proxy-supply = <&mdss_core_gdsc>;

		qcom,proxy-consumer-enable;

		status = "disabled";

	};



	/* GDSCs in GPUCC */

	gpu_gx_sw_reset: syscon@5994008 {

		compatible = "syscon";

		reg = <0x5994008 0x4>;

	};



	gpu_cx_hw_ctrl: syscon@5994540 {

		compatible = "syscon";

		reg = <0x5994540 0x4>;

	};



	gpu_gx_domain_addr: syscon@5994508 {

		compatible = "syscon";

		reg = <0x5994508 0x4>;

	};



	gpu_cx_gdsc: qcom,gdsc@5994064 {

		compatible = "regulator-fixed";

		reg = <0x5994064 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	gpu_gx_gdsc: qcom,gdsc@599400c {

		compatible = "regulator-fixed";

		reg = <0x599400c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;

		domain-addr = <&gpu_gx_domain_addr>;

		qcom,reset-aon-logic;

		status = "disabled";

	};

};

qcom/monaco.dtsi

+101 −0
Original line number Diff line number Diff line 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/qcom,dispcc-monaco.h>

#include <dt-bindings/clock/qcom,gcc-monaco.h>

#include <dt-bindings/clock/qcom,gpucc-monaco.h>



/ {

	model = "Qualcomm Technologies, Inc. Monaco";
@@ -471,8 +475,105 @@ 
			qcom,dump-id = <0x123>;

		};

	};



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			clock-frequency = <38400000>;

			clock-output-names = "xo_board";

			#clock-cells = <0>;

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32000>;

			clock-output-names = "sleep_clk";

			#clock-cells = <0>;

		};

	};



	bi_tcxo: bi_tcxo {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <1>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};



	bi_tcxo_ao: bi_tcxo_ao {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <1>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};



	rpmcc: qcom,rpmcc {

		compatible = "qcom,dummycc";

		clock-output-names = "rpmcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gcc: clock-controller@1410000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	dispcc: clock-controller@5f00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gpucc: clock-controller@5994000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

};



#include "monaco-pinctrl.dtsi"

#include "monaco-ion.dtsi"

#include "monaco-gdsc.dtsi"



&gcc_camss_top_gdsc {

	status = "ok";

};



&gcc_usb20_prim_gdsc {

	status = "ok";

};



&gcc_vcodec0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gcc_venus_gdsc {

	status = "ok";

};



&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {

	status = "ok";

};



&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {

	status = "ok";

};



&mdss_core_gdsc {

	status = "ok";

};



&gpu_cx_gdsc {

	status = "ok";

};



&gpu_gx_gdsc {

	status = "ok";

};