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Commit 17c7c7e7 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7 



not update the dpm table with user's setting

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5be3bb6e

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+6 −4
Original line number Diff line number Diff line
@@ -3588,9 +3588,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons 
			break;

	}



	if (i >= sclk_table->count)

	if (i >= sclk_table->count) {

		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;

	else {

		sclk_table->dpm_levels[i-1].value = sclk;

	} else {

	/* TODO: Check SCLK in DAL's minimum clocks

	 * in case DeepSleep divider update is required.

	 */
@@ -3605,9 +3606,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons 
			break;

	}



	if (i >= mclk_table->count)

	if (i >= mclk_table->count) {

		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;



		mclk_table->dpm_levels[i-1].value = mclk;

	}



	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)

		data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;