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Commit 17a83913 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/powerplay: fix sw SMU wrong UVD/VCE powergate setting 



The UVD/VCE bits are set wrongly. This causes the UVD/VCE clocks
are not brought back correctly on needed.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d6ee400e

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

+6 −6
Original line number Diff line number Diff line
@@ -1835,24 +1835,24 @@ static int smu_v11_0_update_od8_settings(struct smu_context *smu, 


static int smu_v11_0_dpm_set_uvd_enable(struct smu_context *smu, bool enable)

{

	if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))

	if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT))

		return 0;



	if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))

	if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT))

		return 0;



	return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);

	return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);

}



static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)

{

	if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT))

	if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))

		return 0;



	if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT))

	if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))

		return 0;



	return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);

	return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);

}



static int smu_v11_0_get_current_rpm(struct smu_context *smu,