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Commit 17a3714d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add PMIC devices for SA6150"

parents dd3e4ff7 3b525e02
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qcom/pm6155.dtsi

0 → 100644
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#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/qcom,qpnp-power-on.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>

&spmi_bus {
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;

	qcom,pm6155@0 {
		compatible = "qcom,spmi-pmic";
		reg = <0 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <0>;

		pm6155_1_tz: qcom,temp-alarm@2400 {
			compatible = "qcom,spmi-temp-alarm";
			reg = <0x2400>;
			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
			#thermal-sensor-cells = <0>;
			qcom,temperature-threshold-set = <1>;
		};

		qcom,power-on@800 {
			compatible = "qcom,qpnp-power-on";
			reg = <0x800>;
			interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,
				     <0x0 0x8 0x1 IRQ_TYPE_NONE>;
			interrupt-names = "kpdpwr", "resin";
			qcom,pon-dbc-delay = <15625>;
			qcom,kpdpwr-sw-debounce;
			qcom,system-reset;
			qcom,store-hard-reset-reason;

			qcom,pon_1 {
				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
				qcom,pull-up = <1>;
				linux,code = <KEY_POWER>;
			};

			qcom,pon_2 {
				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
				qcom,pull-up;
				linux,code = <KEY_VOLUMEDOWN>;
			};
		};

		pm6155_1_clkdiv: clock-controller@5b00 {
			compatible = "qcom,spmi-clkdiv";
			reg = <0x5b00>;
			#clock-cells = <1>;
			qcom,num-clkdivs = <2>;
			clock-output-names = "pm6155_1_div_clk1",
						"pm6155_1_div_clk2";
			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";
		};

		pm6155_1_rtc: qcom,pm6155_1_rtc {
			compatible = "qcom,pm8941-rtc";
			#address-cells = <1>;
			#size-cells = <1>;
			qcom,qpnp-rtc-write = <0>;
			qcom,qpnp-rtc-alarm-pwrup = <0>;

			qcom,pm6155_1_rtc_rw@6000 {
				reg = <0x6000 0x100>;
			};
			qcom,pm6155_1_rtc_alarm@6100 {
				reg = <0x6100 0x100>;
				interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
			};
		};

		pm6155_1_gpios: pinctrl@c000 {
			compatible = "qcom,pm8150-gpio";
			reg = <0xc000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pm6155_1_sdam_2: sdam@b100 {
			compatible = "qcom,spmi-sdam";
			reg = <0xb100 0x100>;
		};

	};

	qcom,pm6155@1 {
		compatible ="qcom,spmi-pmic";
		reg = <1 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	/* below definitions are for the second instance of pm6155 */
	qcom,pm6155@4 {
		compatible = "qcom,spmi-pmic";
		reg = <4 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,power-on@800 {
			compatible = "qcom,qpnp-power-on";
			reg = <0x800>;
		};

		pm6155_2_clkdiv: clock-controller@5b00 {
			compatible = "qcom,spmi-clkdiv";
			reg = <0x5b00>;
			#clock-cells = <1>;
			qcom,num-clkdivs = <2>;
			clock-output-names = "pm6155_2_div_clk1",
						"pm6155_2_div_clk2";
			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";
		};

		pm6155_2_gpios: pinctrl@c000 {
			compatible = "qcom,pm8150-gpio";
			reg = <0xc000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,pm6155@5 {
		compatible ="qcom,spmi-pmic";
		reg = <5 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&thermal_zones {
	pm6155-1-tz {
		polling-delay-passive = <100>;
		polling-delay = <0>;
		thermal-governor = "step_wise";
		thermal-sensors = <&pm6155_1_tz>;
		wake-capable-sensor;

		trips {
			pm6155_trip0: trip0 {
				temperature = <105000>;
				hysteresis = <0>;
				type = "passive";
			};

			pm6155_trip1: trip1 {
				temperature = <125000>;
				hysteresis = <0>;
				type = "critical";
			};

			trip2 {
				temperature = <155000>;
				hysteresis = <0>;
				type = "critical";
			};
		};
	};
};
+28 −0
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#include "sa6155-adp-common.dtsi"

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qmp-v3-660";

	vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */
	vdda-pll-supply = <&pm6155_1_l12>;
	vdda-phy-max-microamp = <30000>;
	vdda-pll-max-microamp = <12000>;

	status = "ok";
};

&ufshc_mem {
	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm6155_1_l17>;
	vcc-voltage-level = <2950000 2960000>;
	vccq2-supply = <&pm6155_1_s4>;
	vcc-max-microamp = <800000>;
	vccq2-max-microamp = <600000>;

	qcom,vddp-ref-clk-supply = <&pm6155_1_l11>;
	qcom,vddp-ref-clk-max-microamp = <100>;
	qcom,vddp-ref-clk-min-uV = <1232000>;
	qcom,vddp-ref-clk-max-uV = <1260000>;

	status = "ok";
};
+28 −0
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#include "sa6155-adp-common.dtsi"

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qmp-v3-660";

	vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */
	vdda-pll-supply = <&pm6155_1_l12>;
	vdda-phy-max-microamp = <30000>;
	vdda-pll-max-microamp = <12000>;

	status = "ok";
};

&ufshc_mem {
	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm6155_1_l17>;
	vcc-voltage-level = <2950000 2960000>;
	vccq2-supply = <&pm6155_1_s4>;
	vcc-max-microamp = <800000>;
	vccq2-max-microamp = <600000>;

	qcom,vddp-ref-clk-supply = <&pm6155_1_l11>;
	qcom,vddp-ref-clk-max-microamp = <100>;
	qcom,vddp-ref-clk-min-uV = <1232000>;
	qcom,vddp-ref-clk-max-uV = <1260000>;

	status = "ok";
};
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@@ -40,3 +40,4 @@
};

#include "sa6155-regulator.dtsi"
#include "pm6155.dtsi"
+6 −0
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@@ -7,6 +7,12 @@
	qcom,msm-id = <377 0>, <380 0>;
};

/* Delete second instance of pm6155 definitions for APQ version */
&spmi_bus {
	/delete-node/ qcom,pm6155@4;
	/delete-node/ qcom,pm6155@5;
};

&apps_rsc {
	/delete-node/ rpmh-regulator-modemlvl;
	/delete-node/ rpmh-regulator-ldoc2;
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