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Commit 179fdc3f authored by David Woodhouse's avatar David Woodhouse
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[MTD] Basic NAND driver for AMD/NatSemi CS5535/CS5536 Geode companion chip 



This lacks hardware ECC support and a few optimisations we're going to
want fairly soon, but it works well enough to mount and use JFFS2.

Signed-off-by: default avatarDavid Woodhouse <dwmw2@infradead.org>
parent b04ecae3

drivers/mtd/nand/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -189,6 +189,10 @@ config MTD_NAND_SHARPSL 
	tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"

	depends on MTD_NAND && ARCH_PXA



config MTD_NAND_CS553X

	tristate "NAND support for CS5535/CS5536 (AMD Geode companion chip)"

	depends on MTD_NAND && X86_PC && PCI

	

config MTD_NAND_NANDSIM

	tristate "Support for NAND Flash Simulator"

	depends on MTD_NAND && MTD_PARTITIONS

drivers/mtd/nand/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -19,5 +19,6 @@ obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o 
obj-$(CONFIG_MTD_NAND_SHARPSL)		+= sharpsl.o

obj-$(CONFIG_MTD_NAND_TS7250)		+= ts7250.o

obj-$(CONFIG_MTD_NAND_NANDSIM)		+= nandsim.o

obj-$(CONFIG_MTD_NAND_CS553X)		+= cs553x_nand.o



nand-objs = nand_base.o nand_bbt.o

drivers/mtd/nand/cs553x_nand.c

0 → 100644
+293 −0
Original line number Diff line number Diff line 
/*

 * drivers/mtd/nand/cs553x_nand.c

 *

 * (C) 2005, 2006 Red Hat Inc.

 *

 * Author: David Woodhouse <dwmw2@infradead.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 *  Overview:

 *   This is a device driver for the NAND flash controller found on 

 *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.

 *

 */



#include <linux/slab.h>

#include <linux/init.h>

#include <linux/module.h>

#include <linux/delay.h>

#include <linux/pci.h>

#include <linux/mtd/mtd.h>

#include <linux/mtd/nand.h>

#include <linux/mtd/partitions.h>



#include <asm/msr.h>

#include <asm/io.h>



#define NR_CS553X_CONTROLLERS	4



/* NAND Timing MSRs */

#define MSR_NANDF_DATA		0x5140001b	/* NAND Flash Data Timing MSR */

#define MSR_NANDF_CTL		0x5140001c	/* NAND Flash Control Timing */

#define MSR_NANDF_RSVD		0x5140001d	/* Reserved */



/* NAND BAR MSRs */

#define MSR_DIVIL_LBAR_FLSH0	0x51400010	/* Flash Chip Select 0 */

#define MSR_DIVIL_LBAR_FLSH1	0x51400011	/* Flash Chip Select 1 */

#define MSR_DIVIL_LBAR_FLSH2	0x51400012	/* Flash Chip Select 2 */

#define MSR_DIVIL_LBAR_FLSH3	0x51400013	/* Flash Chip Select 3 */

	/* Each made up of... */

#define FLSH_LBAR_EN		(1ULL<<32)

#define FLSH_NOR_NAND		(1ULL<<33)	/* 1 for NAND */

#define FLSH_MEM_IO		(1ULL<<34)	/* 1 for MMIO */

	/* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */

	/* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */



/* Pin function selection MSR (IDE vs. flash on the IDE pins) */

#define MSR_DIVIL_BALL_OPTS	0x51400015

#define PIN_OPT_IDE		(1<<0)		/* 0 for flash, 1 for IDE */



/* Registers within the NAND flash controller BAR -- memory mapped */

#define MM_NAND_DATA		0x00	/* 0 to 0x7ff, in fact */

#define MM_NAND_CTL		0x800	/* Any even address 0x800-0x80e */

#define MM_NAND_IO		0x801	/* Any odd address 0x801-0x80f */

#define MM_NAND_STS		0x810

#define MM_NAND_ECC_LSB		0x811

#define MM_NAND_ECC_MSB		0x812

#define MM_NAND_ECC_COL		0x813

#define MM_NAND_LAC		0x814

#define MM_NAND_ECC_CTL		0x815



/* Registers within the NAND flash controller BAR -- I/O mapped */

#define IO_NAND_DATA		0x00	/* 0 to 3, in fact */

#define IO_NAND_CTL		0x04

#define IO_NAND_IO		0x05

#define IO_NAND_STS		0x06

#define IO_NAND_ECC_CTL		0x08

#define IO_NAND_ECC_LSB		0x09

#define IO_NAND_ECC_MSB		0x0a

#define IO_NAND_ECC_COL		0x0b

#define IO_NAND_LAC		0x0c



#define CS_NAND_CTL_DIST_EN	(1<<4)	/* Enable NAND Distract interrupt */

#define CS_NAND_CTL_RDY_INT_MASK	(1<<3)	/* Enable RDY/BUSY# interrupt */

#define CS_NAND_CTL_ALE		(1<<2)

#define CS_NAND_CTL_CLE		(1<<1)

#define CS_NAND_CTL_CE		(1<<0)	/* Keep low; 1 to reset */



#define CS_NAND_STS_FLASH_RDY	(1<<3)

#define CS_NAND_CTLR_BUSY	(1<<2)

#define CS_NAND_CMD_COMP	(1<<1)

#define CS_NAND_DIST_ST		(1<<0)



#define CS_NAND_ECC_PARITY	(1<<2)

#define CS_NAND_ECC_CLRECC	(1<<1)

#define CS_NAND_ECC_ENECC	(1<<0)



static unsigned char cs553x_read_byte(struct mtd_info *mtd)

{

	struct nand_chip *this = mtd->priv;

	unsigned char foo = readb(this->IO_ADDR_R);

	return foo;

}



static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)

{

	struct nand_chip *this = mtd->priv;

	int i = 100000;



	while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {

		udelay(1);

		i--;

	}

	writeb(byte, this->IO_ADDR_W+0x801);

}



static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd)

{

	struct nand_chip *this = mtd->priv;

	void __iomem *mmio_base = this->IO_ADDR_R;



	uint8_t old = readb(mmio_base + MM_NAND_CTL);



	switch(cmd) {

	case NAND_CTL_SETCLE:

		old |= CS_NAND_CTL_CLE;

		break;



	case NAND_CTL_CLRCLE:

		old &= ~CS_NAND_CTL_CLE;

		break;



	case NAND_CTL_SETALE:

		old |= CS_NAND_CTL_ALE;

		break;



	case NAND_CTL_CLRALE:

		old &= ~CS_NAND_CTL_ALE;

		break;



	case NAND_CTL_SETNCE:

		old &= ~CS_NAND_CTL_CE;

		break;



	case NAND_CTL_CLRNCE:

		old |= CS_NAND_CTL_CE;

		break;

	}

	writeb(old, mmio_base + MM_NAND_CTL);

}





static int cs553x_device_ready(struct mtd_info *mtd)

{

	struct nand_chip *this = mtd->priv;

	void __iomem *mmio_base = this->IO_ADDR_R;

	unsigned char foo = readb(mmio_base + MM_NAND_STS);



	return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY); 

}



static struct mtd_info *cs553x_mtd[4];



static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)

{

	int err = 0;

	struct nand_chip *this;

	struct mtd_info *new_mtd;



	printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);



	if (!mmio) {

		printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");

		return -ENXIO;

	}



	/* Allocate memory for MTD device structure and private data */

	new_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);

	if (!new_mtd) {

		printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");

		err = -ENOMEM;

		goto out;

	}



	/* Get pointer to private data */

	this = (struct nand_chip *) (&new_mtd[1]);



	/* Initialize structures */

	memset((char *) new_mtd, 0, sizeof(struct mtd_info));

	memset((char *) this, 0, sizeof(struct nand_chip));



	/* Link the private data with the MTD structure */

	new_mtd->priv = this;



	/* map physical address */

	this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);

	if (!this->IO_ADDR_R) {

		printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);

		err = -EIO;

		goto out_mtd;

	}



	this->hwcontrol = cs553x_hwcontrol;

	this->dev_ready = cs553x_device_ready;

	this->read_byte = cs553x_read_byte;

	this->write_byte = cs553x_write_byte;



	/* 20 us command delay time */

	this->chip_delay = 20;

	this->eccmode = NAND_ECC_SOFT;



	/* Enable the following for a flash based bad block table */

	//	this->options = NAND_USE_FLASH_BBT;



	/* Scan to find existance of the device */

	if (nand_scan (new_mtd, 1)) {

		err = -ENXIO;

		goto out_ior;

	}



	cs553x_mtd[cs] = new_mtd;

	goto out;



out_ior:

	iounmap((void *)this->IO_ADDR_R);

out_mtd:

	kfree (new_mtd);

out:

	return err;

}



int __init cs553x_init(void)

{

	int err = -ENXIO;

	int i;

	uint64_t val;



	/* Check whether we actually have a CS5535 or CS5536 */

	if (!pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, NULL) &&

	    !pci_find_device(PCI_VENDOR_ID_NS,  PCI_DEVICE_ID_NS_CS5535_ISA, NULL))

		return -ENXIO;



	rdmsrl(MSR_DIVIL_BALL_OPTS, val);

	if (val & 1) {

		printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");

		return -ENXIO;

	}



	for (i=0; i<NR_CS553X_CONTROLLERS; i++) {

		rdmsrl(MSR_DIVIL_LBAR_FLSH0+i, val);



		if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))

			err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);

	}

	

	/* Register all devices together here. This means we can easily hack it to 

	   do mtdconcat etc. if we want to. */

	for (i=0; i<NR_CS553X_CONTROLLERS; i++) {

		if (cs553x_mtd[i]) {

			add_mtd_device(cs553x_mtd[i]);



			/* If any devices registered, return success. Else the last error. */

			err = 0;

		}

	}



	return err;

}

module_init(cs553x_init);



static void __exit cs553x_cleanup (void)

{

	int i;



	for (i=0; i<NR_CS553X_CONTROLLERS; i++) {

		struct mtd_info *mtd = cs553x_mtd[i];

		struct nand_chip *this;

		void __iomem *mmio_base;



		if (!mtd)

			break;



		this = cs553x_mtd[i]->priv;

		mmio_base = this->IO_ADDR_R;



		/* Release resources, unregister device */

		nand_release (cs553x_mtd[i]);

		cs553x_mtd[i] = NULL;



		/* unmap physical adress */

		iounmap(mmio_base);



		/* Free the MTD device structure */

		kfree (mtd);

	}

}

module_exit(cs553x_cleanup);



MODULE_LICENSE("GPL");

MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");

MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");