Unverified Commit 1760debb authored Jul 24, 2018 by Palmer Dabbelt

RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}



These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.

Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 84df9525

arch/riscv/kernel/cacheinfo.c

+0 −7

Original line number	Diff line number	Diff line
		@@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
		{
		this_leaf->level = level;
		this_leaf->type = type;
		/* not a sector cache */
		this_leaf->physical_line_partition = 1;
		/* TODO: Add to DTS */
		this_leaf->attributes =
		CACHE_WRITE_BACK
		\| CACHE_READ_ALLOCATE
		\| CACHE_WRITE_ALLOCATE;
		}

		static int __init_cache_level(unsigned int cpu)