Merge branch 'pm-next' of... (172c1135) · Commits · e / devices / android_kernel_fairphone_FP5

arch/arm/mach-omap2/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -87,6 +87,7 @@ obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
		obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o
		obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o
		obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
		obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o

		# EMU peripherals
		obj-$(CONFIG_OMAP3_EMU) += emu.o

arch/arm/mach-omap2/clockdomain.c

+15 −95

Original line number	Diff line number	Diff line
		@@ -258,97 +258,6 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)

		}

		/**
		* _init_wkdep_usecount - initialize wkdep usecounts to match hardware
		* @clkdm: clockdomain to initialize wkdep usecounts
		*
		* Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
		* If a wakeup dependency is present in the hardware, the usecount will be
		* set to 1; otherwise, it will be set to 0. Software should clear all
		* software wakeup dependencies prior to calling this function if it wishes
		* to ensure that all usecounts start at 0. No return value.
		*/
		static void _init_wkdep_usecount(struct clockdomain *clkdm)
		{
		u32 v;
		struct clkdm_dep *cd;

		if (!clkdm->wkdep_srcs)
		return;

		for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
		if (!omap_chip_is(cd->omap_chip))
		continue;

		if (!cd->clkdm && cd->clkdm_name)
		cd->clkdm = _clkdm_lookup(cd->clkdm_name);

		if (!cd->clkdm) {
		WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
		"found\n", clkdm->name, cd->clkdm_name);
		continue;
		}

		v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
		PM_WKDEP,
		(1 << cd->clkdm->dep_bit));

		if (v)
		pr_debug("clockdomain: %s: wakeup dependency already "
		"set to wake up when %s wakes\n",
		clkdm->name, cd->clkdm->name);

		atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
		}
		}

		/**
		* _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
		* @clkdm: clockdomain to initialize sleepdep usecounts
		*
		* Initialize the sleep dependency usecount variables for clockdomain @clkdm.
		* If a sleep dependency is present in the hardware, the usecount will be
		* set to 1; otherwise, it will be set to 0. Software should clear all
		* software sleep dependencies prior to calling this function if it wishes
		* to ensure that all usecounts start at 0. No return value.
		*/
		static void _init_sleepdep_usecount(struct clockdomain *clkdm)
		{
		u32 v;
		struct clkdm_dep *cd;

		if (!cpu_is_omap34xx())
		return;

		if (!clkdm->sleepdep_srcs)
		return;

		for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
		if (!omap_chip_is(cd->omap_chip))
		continue;

		if (!cd->clkdm && cd->clkdm_name)
		cd->clkdm = _clkdm_lookup(cd->clkdm_name);

		if (!cd->clkdm) {
		WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
		"not found\n", clkdm->name, cd->clkdm_name);
		continue;
		}

		v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
		OMAP3430_CM_SLEEPDEP,
		(1 << cd->clkdm->dep_bit));

		if (v)
		pr_debug("clockdomain: %s: sleep dependency already "
		"set to prevent from idling until %s "
		"idles\n", clkdm->name, cd->clkdm->name);

		atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
		}
		};

		/* Public functions */

		/**
		@@ -379,12 +288,17 @@ void clkdm_init(struct clockdomain **clkdms,
		_autodep_lookup(autodep);

		/*
		* Ensure that the *dep_usecount registers reflect the current
		* state of the PRCM.
		* Put all clockdomains into software-supervised mode; PM code
		* should later enable hardware-supervised mode as appropriate
		*/
		list_for_each_entry(clkdm, &clkdm_list, node) {
		_init_wkdep_usecount(clkdm);
		_init_sleepdep_usecount(clkdm);
		if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
		omap2_clkdm_wakeup(clkdm);
		else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
		omap2_clkdm_deny_idle(clkdm);

		clkdm_clear_all_wkdeps(clkdm);
		clkdm_clear_all_sleepdeps(clkdm);
		}
		}

		@@ -592,6 +506,9 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
		if (!omap_chip_is(cd->omap_chip))
		continue;

		if (!cd->clkdm && cd->clkdm_name)
		cd->clkdm = _clkdm_lookup(cd->clkdm_name);

		/* PRM accesses are slow, so minimize them */
		mask \|= 1 << cd->clkdm->dep_bit;
		atomic_set(&cd->wkdep_usecount, 0);
		@@ -752,6 +669,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
		if (!omap_chip_is(cd->omap_chip))
		continue;

		if (!cd->clkdm && cd->clkdm_name)
		cd->clkdm = _clkdm_lookup(cd->clkdm_name);

		/* PRM accesses are slow, so minimize them */
		mask \|= 1 << cd->clkdm->dep_bit;
		atomic_set(&cd->sleepdep_usecount, 0);

arch/arm/mach-omap2/cpuidle34xx.c

+55 −3

Original line number	Diff line number	Diff line
		@@ -60,7 +60,8 @@ struct omap3_processor_cx {

		struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
		struct omap3_processor_cx current_cx_state;
		struct powerdomain mpu_pd, core_pd;
		struct powerdomain mpu_pd, core_pd, *per_pd;
		struct powerdomain *cam_pd;

		/*
		* The latencies/thresholds for various C states have
		@@ -233,14 +234,62 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
		struct cpuidle_state *state)
		{
		struct cpuidle_state *new_state = next_valid_state(dev, state);
		u32 core_next_state, per_next_state = 0, per_saved_state = 0;
		u32 cam_state;
		struct omap3_processor_cx *cx;
		int ret;

		if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
		BUG_ON(!dev->safe_state);
		new_state = dev->safe_state;
		goto select_state;
		}

		cx = cpuidle_get_statedata(state);
		core_next_state = cx->core_state;

		/*
		* FIXME: we currently manage device-specific idle states
		* for PER and CORE in combination with CPU-specific
		* idle states. This is wrong, and device-specific
		* idle managment needs to be separated out into
		* its own code.
		*/

		/*
		* Prevent idle completely if CAM is active.
		* CAM does not have wakeup capability in OMAP3.
		*/
		cam_state = pwrdm_read_pwrst(cam_pd);
		if (cam_state == PWRDM_POWER_ON) {
		new_state = dev->safe_state;
		goto select_state;
		}

		/*
		* Prevent PER off if CORE is not in retention or off as this
		* would disable PER wakeups completely.
		*/
		per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
		if ((per_next_state == PWRDM_POWER_OFF) &&
		(core_next_state > PWRDM_POWER_RET)) {
		per_next_state = PWRDM_POWER_RET;
		pwrdm_set_next_pwrst(per_pd, per_next_state);
		}

		/* Are we changing PER target state? */
		if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

		select_state:
		dev->last_state = new_state;
		return omap3_enter_idle(dev, new_state);
		ret = omap3_enter_idle(dev, new_state);

		/* Restore original PER state if it was modified */
		if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

		return ret;
		}

		DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
		@@ -328,7 +377,8 @@ void omap_init_power_states(void)
		cpuidle_params_table[OMAP3_STATE_C2].threshold;
		omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
		omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
		omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
		omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID \|
		CPUIDLE_FLAG_CHECK_BM;

		/* C3 . MPU CSWR + Core inactive */
		omap3_power_states[OMAP3_STATE_C3].valid =
		@@ -426,6 +476,8 @@ int __init omap3_idle_init(void)

		mpu_pd = pwrdm_lookup("mpu_pwrdm");
		core_pd = pwrdm_lookup("core_pwrdm");
		per_pd = pwrdm_lookup("per_pwrdm");
		cam_pd = pwrdm_lookup("cam_pwrdm");

		omap_init_power_states();
		cpuidle_register_driver(&omap3_idle_driver);

arch/arm/mach-omap2/io.c

+4 −3

Original line number	Diff line number	Diff line
		@@ -323,6 +323,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
		omap2430_hwmod_init();
		else if (cpu_is_omap34xx())
		omap3xxx_hwmod_init();
		else if (cpu_is_omap44xx())
		omap44xx_hwmod_init();

		/* The OPP tables have to be registered before a clk init */
		omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);

		@@ -342,9 +345,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
		#ifndef CONFIG_PM_RUNTIME
		skip_setup_idle = 1;
		#endif
		if (cpu_is_omap24xx() \|\| cpu_is_omap34xx()) /* FIXME: OMAP4 */
		omap_hwmod_late_init(skip_setup_idle);

		if (cpu_is_omap24xx() \|\| cpu_is_omap34xx()) {
		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
		_omap2_init_reprogram_sdrc();

arch/arm/mach-omap2/omap_hwmod_44xx_data.c

0 → 100644

+482 −0

Original line number	Diff line number	Diff line
		/*
		* Hardware modules present on the OMAP44xx chips
		*
		* Copyright (C) 2009-2010 Texas Instruments, Inc.
		* Copyright (C) 2009-2010 Nokia Corporation
		*
		* Paul Walmsley
		* Benoit Cousson
		*
		* This file is automatically generated from the OMAP hardware databases.
		* We respectfully ask that any modifications to this file be coordinated
		* with the public linux-omap@vger.kernel.org mailing list and the
		* authors above to ensure that the autogeneration scripts are kept
		* up-to-date with the file contents.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/

		#include <linux/io.h>

		#include <plat/omap_hwmod.h>
		#include <plat/cpu.h>

		#include "omap_hwmod_common_data.h"

		#include "cm.h"
		#include "prm-regbits-44xx.h"

		/* Base offset for all OMAP4 interrupts external to MPUSS */
		#define OMAP44XX_IRQ_GIC_START 32

		/* Base offset for all OMAP4 dma requests */
		#define OMAP44XX_DMA_REQ_START 1

		/* Backward references (IPs with Bus Master capability) */
		static struct omap_hwmod omap44xx_dmm_hwmod;
		static struct omap_hwmod omap44xx_emif_fw_hwmod;
		static struct omap_hwmod omap44xx_l3_instr_hwmod;
		static struct omap_hwmod omap44xx_l3_main_1_hwmod;
		static struct omap_hwmod omap44xx_l3_main_2_hwmod;
		static struct omap_hwmod omap44xx_l3_main_3_hwmod;
		static struct omap_hwmod omap44xx_l4_abe_hwmod;
		static struct omap_hwmod omap44xx_l4_cfg_hwmod;
		static struct omap_hwmod omap44xx_l4_per_hwmod;
		static struct omap_hwmod omap44xx_l4_wkup_hwmod;
		static struct omap_hwmod omap44xx_mpu_hwmod;
		static struct omap_hwmod omap44xx_mpu_private_hwmod;

		/*
		* Interconnects omap_hwmod structures
		* hwmods that compose the global OMAP interconnect
		*/

		/*
		* 'dmm' class
		* instance(s): dmm
		*/
		static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
		.name = "dmm",
		};

		/* dmm interface data */
		/* l3_main_1 -> dmm */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
		.master = &omap44xx_l3_main_1_hwmod,
		.slave = &omap44xx_dmm_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* mpu -> dmm */
		static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
		.master = &omap44xx_mpu_hwmod,
		.slave = &omap44xx_dmm_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* dmm slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
		&omap44xx_l3_main_1__dmm,
		&omap44xx_mpu__dmm,
		};

		static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
		{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
		};

		static struct omap_hwmod omap44xx_dmm_hwmod = {
		.name = "dmm",
		.class = &omap44xx_dmm_hwmod_class,
		.slaves = omap44xx_dmm_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
		.mpu_irqs = omap44xx_dmm_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/*
		* 'emif_fw' class
		* instance(s): emif_fw
		*/
		static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
		.name = "emif_fw",
		};

		/* emif_fw interface data */
		/* dmm -> emif_fw */
		static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
		.master = &omap44xx_dmm_hwmod,
		.slave = &omap44xx_emif_fw_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_cfg -> emif_fw */
		static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
		.master = &omap44xx_l4_cfg_hwmod,
		.slave = &omap44xx_emif_fw_hwmod,
		.clk = "l4_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* emif_fw slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
		&omap44xx_dmm__emif_fw,
		&omap44xx_l4_cfg__emif_fw,
		};

		static struct omap_hwmod omap44xx_emif_fw_hwmod = {
		.name = "emif_fw",
		.class = &omap44xx_emif_fw_hwmod_class,
		.slaves = omap44xx_emif_fw_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/*
		* 'l3' class
		* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
		*/
		static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
		.name = "l3",
		};

		/* l3_instr interface data */
		/* l3_main_3 -> l3_instr */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
		.master = &omap44xx_l3_main_3_hwmod,
		.slave = &omap44xx_l3_instr_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_instr slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
		&omap44xx_l3_main_3__l3_instr,
		};

		static struct omap_hwmod omap44xx_l3_instr_hwmod = {
		.name = "l3_instr",
		.class = &omap44xx_l3_hwmod_class,
		.slaves = omap44xx_l3_instr_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/* l3_main_2 -> l3_main_1 */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
		.master = &omap44xx_l3_main_2_hwmod,
		.slave = &omap44xx_l3_main_1_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_cfg -> l3_main_1 */
		static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
		.master = &omap44xx_l4_cfg_hwmod,
		.slave = &omap44xx_l3_main_1_hwmod,
		.clk = "l4_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* mpu -> l3_main_1 */
		static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
		.master = &omap44xx_mpu_hwmod,
		.slave = &omap44xx_l3_main_1_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main_1 slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
		&omap44xx_l3_main_2__l3_main_1,
		&omap44xx_l4_cfg__l3_main_1,
		&omap44xx_mpu__l3_main_1,
		};

		static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
		.name = "l3_main_1",
		.class = &omap44xx_l3_hwmod_class,
		.slaves = omap44xx_l3_main_1_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/* l3_main_2 interface data */
		/* l3_main_1 -> l3_main_2 */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
		.master = &omap44xx_l3_main_1_hwmod,
		.slave = &omap44xx_l3_main_2_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_cfg -> l3_main_2 */
		static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
		.master = &omap44xx_l4_cfg_hwmod,
		.slave = &omap44xx_l3_main_2_hwmod,
		.clk = "l4_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main_2 slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
		&omap44xx_l3_main_1__l3_main_2,
		&omap44xx_l4_cfg__l3_main_2,
		};

		static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
		.name = "l3_main_2",
		.class = &omap44xx_l3_hwmod_class,
		.slaves = omap44xx_l3_main_2_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/* l3_main_3 interface data */
		/* l3_main_1 -> l3_main_3 */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
		.master = &omap44xx_l3_main_1_hwmod,
		.slave = &omap44xx_l3_main_3_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main_2 -> l3_main_3 */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
		.master = &omap44xx_l3_main_2_hwmod,
		.slave = &omap44xx_l3_main_3_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_cfg -> l3_main_3 */
		static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
		.master = &omap44xx_l4_cfg_hwmod,
		.slave = &omap44xx_l3_main_3_hwmod,
		.clk = "l4_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main_3 slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
		&omap44xx_l3_main_1__l3_main_3,
		&omap44xx_l3_main_2__l3_main_3,
		&omap44xx_l4_cfg__l3_main_3,
		};

		static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
		.name = "l3_main_3",
		.class = &omap44xx_l3_hwmod_class,
		.slaves = omap44xx_l3_main_3_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/*
		* 'l4' class
		* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
		*/
		static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
		.name = "l4",
		};

		/* l4_abe interface data */
		/* l3_main_1 -> l4_abe */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
		.master = &omap44xx_l3_main_1_hwmod,
		.slave = &omap44xx_l4_abe_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* mpu -> l4_abe */
		static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
		.master = &omap44xx_mpu_hwmod,
		.slave = &omap44xx_l4_abe_hwmod,
		.clk = "ocp_abe_iclk",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_abe slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
		&omap44xx_l3_main_1__l4_abe,
		&omap44xx_mpu__l4_abe,
		};

		static struct omap_hwmod omap44xx_l4_abe_hwmod = {
		.name = "l4_abe",
		.class = &omap44xx_l4_hwmod_class,
		.slaves = omap44xx_l4_abe_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/* l4_cfg interface data */
		/* l3_main_1 -> l4_cfg */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
		.master = &omap44xx_l3_main_1_hwmod,
		.slave = &omap44xx_l4_cfg_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_cfg slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
		&omap44xx_l3_main_1__l4_cfg,
		};

		static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
		.name = "l4_cfg",
		.class = &omap44xx_l4_hwmod_class,
		.slaves = omap44xx_l4_cfg_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/* l4_per interface data */
		/* l3_main_2 -> l4_per */
		static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
		.master = &omap44xx_l3_main_2_hwmod,
		.slave = &omap44xx_l4_per_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_per slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
		&omap44xx_l3_main_2__l4_per,
		};

		static struct omap_hwmod omap44xx_l4_per_hwmod = {
		.name = "l4_per",
		.class = &omap44xx_l4_hwmod_class,
		.slaves = omap44xx_l4_per_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/* l4_wkup interface data */
		/* l4_cfg -> l4_wkup */
		static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
		.master = &omap44xx_l4_cfg_hwmod,
		.slave = &omap44xx_l4_wkup_hwmod,
		.clk = "l4_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l4_wkup slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
		&omap44xx_l4_cfg__l4_wkup,
		};

		static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
		.name = "l4_wkup",
		.class = &omap44xx_l4_hwmod_class,
		.slaves = omap44xx_l4_wkup_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/*
		* 'mpu_bus' class
		* instance(s): mpu_private
		*/
		static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
		.name = "mpu_bus",
		};

		/* mpu_private interface data */
		/* mpu -> mpu_private */
		static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
		.master = &omap44xx_mpu_hwmod,
		.slave = &omap44xx_mpu_private_hwmod,
		.clk = "l3_div_ck",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* mpu_private slave ports */
		static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
		&omap44xx_mpu__mpu_private,
		};

		static struct omap_hwmod omap44xx_mpu_private_hwmod = {
		.name = "mpu_private",
		.class = &omap44xx_mpu_bus_hwmod_class,
		.slaves = omap44xx_mpu_private_slaves,
		.slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		/*
		* 'mpu' class
		* mpu sub-system
		*/

		static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
		.name = "mpu",
		};

		/* mpu */
		static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
		{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
		{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
		{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
		};

		/* mpu master ports */
		static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
		&omap44xx_mpu__l3_main_1,
		&omap44xx_mpu__l4_abe,
		&omap44xx_mpu__dmm,
		};

		static struct omap_hwmod omap44xx_mpu_hwmod = {
		.name = "mpu",
		.class = &omap44xx_mpu_hwmod_class,
		.flags = (HWMOD_INIT_NO_IDLE \| HWMOD_INIT_NO_RESET),
		.mpu_irqs = omap44xx_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
		.main_clk = "dpll_mpu_m2_ck",
		.prcm = {
		.omap4 = {
		.clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
		},
		},
		.masters = omap44xx_mpu_masters,
		.masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
		};

		static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
		/* dmm class */
		&omap44xx_dmm_hwmod,
		/* emif_fw class */
		&omap44xx_emif_fw_hwmod,
		/* l3 class */
		&omap44xx_l3_instr_hwmod,
		&omap44xx_l3_main_1_hwmod,
		&omap44xx_l3_main_2_hwmod,
		&omap44xx_l3_main_3_hwmod,
		/* l4 class */
		&omap44xx_l4_abe_hwmod,
		&omap44xx_l4_cfg_hwmod,
		&omap44xx_l4_per_hwmod,
		&omap44xx_l4_wkup_hwmod,
		/* mpu_bus class */
		&omap44xx_mpu_private_hwmod,

		/* mpu class */
		&omap44xx_mpu_hwmod,
		NULL,
		};

		int __init omap44xx_hwmod_init(void)
		{
		return omap_hwmod_init(omap44xx_hwmods);
		}