Commit 1719b9c0 authored Oct 12, 2022 by Mauro Lima Committed by Greg Kroah-Hartman Nov 25, 2022

spi: intel: Fix the offset to get the 64K erase opcode



[ Upstream commit 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 ]

According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.

Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com


Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent af93d7c9

drivers/mtd/spi-nor/intel-spi.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -113,7 +113,7 @@
		#define ERASE_OPCODE_SHIFT 8
		#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
		#define ERASE_64K_OPCODE_SHIFT 16
		#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
		#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)

		#define INTEL_SPI_TIMEOUT 5000 /* ms */
		#define INTEL_SPI_FIFO_SZ 64