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Commit 16eeaec7 authored by Boris Brezillon's avatar Boris Brezillon Committed by Mike Turquette
Browse files

clk: at91: fix div by zero in USB clock driver 



Test rate value before calculating the div value to avoid div by zero.

Signed-off-by: default avatarBoris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: default avatarGaël PORTAY <gael.portay@gmail.com>
Tested-by: default avatarGaël PORTAY <gael.portay@gmail.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 13a6073d

drivers/clk/at91/clk-usb.c

+5 −2
Original line number Diff line number Diff line
@@ -279,10 +279,13 @@ static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, 
	int i;

	struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);

	struct at91_pmc *pmc = usb->pmc;

	unsigned long div = parent_rate / rate;

	unsigned long div;



	if (parent_rate % rate)

	if (!rate || parent_rate % rate)

		return -EINVAL;



	div = parent_rate / rate;



	for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {

		if (usb->divisors[i] == div) {

			tmp = pmc_read(pmc, AT91_CKGR_PLLBR) &