Commit 162fb9a2 authored May 28, 2021 by Mike Tipton

clk: qcom: clk-cpu-sdxlemur: Use correct PLL ops



The SDXLEMUR CPU PLL uses a non-standard sequence for latching new
configurations. Using the standard lucid_5lpe ops for this PLL means the
latch won't be asserted and the PLL will run at the original frequency
from before the update.

Change-Id: Ia1cb8b7fd116e17a937b961e5907082097e27bfd
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>

parent f65f53d3

drivers/clk/qcom/clk-cpu-sdxlemur.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -306,7 +306,7 @@ static struct clk_alpha_pll apcs_cpu_pll = {
		.fw_name = "bi_tcxo_ao",
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_5lpe_ops,
		.ops = &clk_alpha_pll_lucid_5lpe_sdx_cpu_ops,
		},
		.vdd_data = {
		.vdd_class = &vdd_pll,