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Commit 15fa98e4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'staging-5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging 

Pull staging / IIO driver fixes from Greg KH:
 "Here are some small staging and IIO driver fixes for 5.3-rc4.

  Nothing major, just resolutions for a number of small reported issues,
  full details in the shortlog.

  All have been in linux-next for a while with no reported issues"

* tag 'staging-5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
  iio: adc: gyroadc: fix uninitialized return code
  docs: generic-counter.rst: fix broken references for ABI file
  staging: android: ion: Bail out upon SIGKILL when allocating memory.
  Staging: fbtft: Fix GPIO handling
  staging: unisys: visornic: Update the description of 'poll_for_irq()'
  staging: wilc1000: flush the workqueue before deinit the host
  staging: gasket: apex: fix copy-paste typo
  Staging: fbtft: Fix reset assertion when using gpio descriptor
  Staging: fbtft: Fix probing of gpio descriptor
  iio: imu: mpu6050: add missing available scan masks
  iio: cros_ec_accel_legacy: Fix incorrect channel setting
  IIO: Ingenic JZ47xx: Set clock divider on probe
  iio: adc: max9611: Fix misuse of GENMASK macro
parents 1041f509 09f6109f

drivers/iio/accel/cros_ec_accel_legacy.c

+0 −1
Original line number Diff line number Diff line
@@ -319,7 +319,6 @@ static const struct iio_chan_spec_ext_info cros_ec_accel_legacy_ext_info[] = { 
		.modified = 1,					        \

		.info_mask_separate =					\

			BIT(IIO_CHAN_INFO_RAW) |			\

			BIT(IIO_CHAN_INFO_SCALE) |			\

			BIT(IIO_CHAN_INFO_CALIBBIAS),			\

		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE),	\

		.ext_info = cros_ec_accel_legacy_ext_info,		\

drivers/iio/adc/ingenic-adc.c

+54 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/iio/iio.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/mutex.h>

#include <linux/platform_device.h>
@@ -22,8 +23,11 @@ 
#define JZ_ADC_REG_ADTCH		0x18

#define JZ_ADC_REG_ADBDAT		0x1c

#define JZ_ADC_REG_ADSDAT		0x20

#define JZ_ADC_REG_ADCLK		0x28



#define JZ_ADC_REG_CFG_BAT_MD		BIT(4)

#define JZ_ADC_REG_ADCLK_CLKDIV_LSB	0

#define JZ_ADC_REG_ADCLK_CLKDIV10US_LSB	16



#define JZ_ADC_AUX_VREF				3300

#define JZ_ADC_AUX_VREF_BITS			12
@@ -34,6 +38,8 @@ 
#define JZ4740_ADC_BATTERY_HIGH_VREF		(7500 * 0.986)

#define JZ4740_ADC_BATTERY_HIGH_VREF_BITS	12



struct ingenic_adc;



struct ingenic_adc_soc_data {

	unsigned int battery_high_vref;

	unsigned int battery_high_vref_bits;
@@ -41,6 +47,7 @@ struct ingenic_adc_soc_data { 
	size_t battery_raw_avail_size;

	const int *battery_scale_avail;

	size_t battery_scale_avail_size;

	int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);

};



struct ingenic_adc {
@@ -151,6 +158,42 @@ static const int jz4740_adc_battery_scale_avail[] = { 
	JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,

};



static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)

{

	struct clk *parent_clk;

	unsigned long parent_rate, rate;

	unsigned int div_main, div_10us;



	parent_clk = clk_get_parent(adc->clk);

	if (!parent_clk) {

		dev_err(dev, "ADC clock has no parent\n");

		return -ENODEV;

	}

	parent_rate = clk_get_rate(parent_clk);



	/*

	 * The JZ4725B ADC works at 500 kHz to 8 MHz.

	 * We pick the highest rate possible.

	 * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.

	 */

	div_main = DIV_ROUND_UP(parent_rate, 8000000);

	div_main = clamp(div_main, 1u, 64u);

	rate = parent_rate / div_main;

	if (rate < 500000 || rate > 8000000) {

		dev_err(dev, "No valid divider for ADC main clock\n");

		return -EINVAL;

	}



	/* We also need a divider that produces a 10us clock. */

	div_10us = DIV_ROUND_UP(rate, 100000);



	writel(((div_10us - 1) << JZ_ADC_REG_ADCLK_CLKDIV10US_LSB) |

	       (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,

	       adc->base + JZ_ADC_REG_ADCLK);



	return 0;

}



static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {

	.battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,

	.battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
@@ -158,6 +201,7 @@ static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = { 
	.battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),

	.battery_scale_avail = jz4725b_adc_battery_scale_avail,

	.battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),

	.init_clk_div = jz4725b_adc_init_clk_div,

};



static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
@@ -167,6 +211,7 @@ static const struct ingenic_adc_soc_data jz4740_adc_soc_data = { 
	.battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),

	.battery_scale_avail = jz4740_adc_battery_scale_avail,

	.battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),

	.init_clk_div = NULL, /* no ADCLK register on JZ4740 */

};



static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
@@ -317,6 +362,15 @@ static int ingenic_adc_probe(struct platform_device *pdev) 
		return ret;

	}



	/* Set clock dividers. */

	if (soc_data->init_clk_div) {

		ret = soc_data->init_clk_div(dev, adc);

		if (ret) {

			clk_disable_unprepare(adc->clk);

			return ret;

		}

	}



	/* Put hardware in a known passive state. */

	writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);

	writeb(0xff, adc->base + JZ_ADC_REG_CTRL);

drivers/iio/adc/max9611.c

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ 
#define MAX9611_TEMP_MAX_POS		0x7f80

#define MAX9611_TEMP_MAX_NEG		0xff80

#define MAX9611_TEMP_MIN_NEG		0xd980

#define MAX9611_TEMP_MASK		GENMASK(7, 15)

#define MAX9611_TEMP_MASK		GENMASK(15, 7)

#define MAX9611_TEMP_SHIFT		0x07

#define MAX9611_TEMP_RAW(_r)		((_r) >> MAX9611_TEMP_SHIFT)

#define MAX9611_TEMP_SCALE_NUM		1000000

drivers/iio/adc/rcar-gyroadc.c

+2 −2
Original line number Diff line number Diff line
@@ -382,7 +382,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev) 
				dev_err(dev,

					"Only %i channels supported with %pOFn, but reg = <%i>.\n",

					num_channels, child, reg);

				return ret;

				return -EINVAL;

			}

		}
@@ -391,7 +391,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev) 
			dev_err(dev,

				"Channel %i uses different ADC mode than the rest.\n",

				reg);

			return ret;

			return -EINVAL;

		}



		/* Channel is valid, grab the regulator. */

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

+43 −0
Original line number Diff line number Diff line
@@ -845,6 +845,25 @@ static const struct iio_chan_spec inv_mpu_channels[] = { 
	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),

};



static const unsigned long inv_mpu_scan_masks[] = {

	/* 3-axis accel */

	BIT(INV_MPU6050_SCAN_ACCL_X)

		| BIT(INV_MPU6050_SCAN_ACCL_Y)

		| BIT(INV_MPU6050_SCAN_ACCL_Z),

	/* 3-axis gyro */

	BIT(INV_MPU6050_SCAN_GYRO_X)

		| BIT(INV_MPU6050_SCAN_GYRO_Y)

		| BIT(INV_MPU6050_SCAN_GYRO_Z),

	/* 6-axis accel + gyro */

	BIT(INV_MPU6050_SCAN_ACCL_X)

		| BIT(INV_MPU6050_SCAN_ACCL_Y)

		| BIT(INV_MPU6050_SCAN_ACCL_Z)

		| BIT(INV_MPU6050_SCAN_GYRO_X)

		| BIT(INV_MPU6050_SCAN_GYRO_Y)

		| BIT(INV_MPU6050_SCAN_GYRO_Z),

	0,

};



static const struct iio_chan_spec inv_icm20602_channels[] = {

	IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP),

	{
@@ -871,6 +890,28 @@ static const struct iio_chan_spec inv_icm20602_channels[] = { 
	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z),

};



static const unsigned long inv_icm20602_scan_masks[] = {

	/* 3-axis accel + temp (mandatory) */

	BIT(INV_ICM20602_SCAN_ACCL_X)

		| BIT(INV_ICM20602_SCAN_ACCL_Y)

		| BIT(INV_ICM20602_SCAN_ACCL_Z)

		| BIT(INV_ICM20602_SCAN_TEMP),

	/* 3-axis gyro + temp (mandatory) */

	BIT(INV_ICM20602_SCAN_GYRO_X)

		| BIT(INV_ICM20602_SCAN_GYRO_Y)

		| BIT(INV_ICM20602_SCAN_GYRO_Z)

		| BIT(INV_ICM20602_SCAN_TEMP),

	/* 6-axis accel + gyro + temp (mandatory) */

	BIT(INV_ICM20602_SCAN_ACCL_X)

		| BIT(INV_ICM20602_SCAN_ACCL_Y)

		| BIT(INV_ICM20602_SCAN_ACCL_Z)

		| BIT(INV_ICM20602_SCAN_GYRO_X)

		| BIT(INV_ICM20602_SCAN_GYRO_Y)

		| BIT(INV_ICM20602_SCAN_GYRO_Z)

		| BIT(INV_ICM20602_SCAN_TEMP),

	0,

};



/*

 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and

 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the
@@ -1130,9 +1171,11 @@ int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 
	if (chip_type == INV_ICM20602) {

		indio_dev->channels = inv_icm20602_channels;

		indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels);

		indio_dev->available_scan_masks = inv_icm20602_scan_masks;

	} else {

		indio_dev->channels = inv_mpu_channels;

		indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);

		indio_dev->available_scan_masks = inv_mpu_scan_masks;

	}



	indio_dev->info = &mpu_info;