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Commit 15f33549 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Greg Kroah-Hartman
Browse files

clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents 



[ Upstream commit 60ca4670fd6436c07cea38472ebcee3b00f03bc7 ]

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-32-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Stable-dep-of: 7138c244fb29 ("clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 141ccc12

drivers/clk/qcom/gcc-sm8150.c

+48 −48
Original line number Diff line number Diff line
@@ -250,7 +250,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_cpuss_ahb_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -273,7 +273,7 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_emac_ptp_clk_src",

		.parent_data = gcc_parents_5,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parents_5),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -299,7 +299,7 @@ static struct clk_rcg2 gcc_emac_rgmii_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_emac_rgmii_clk_src",

		.parent_data = gcc_parents_5,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parents_5),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -323,7 +323,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_gp1_clk_src",

		.parent_data = gcc_parents_1,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parents_1),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -338,7 +338,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_gp2_clk_src",

		.parent_data = gcc_parents_1,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parents_1),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -353,7 +353,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_gp3_clk_src",

		.parent_data = gcc_parents_1,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parents_1),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -374,7 +374,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_pcie_0_aux_clk_src",

		.parent_data = gcc_parents_2,

		.num_parents = 3,

		.num_parents = ARRAY_SIZE(gcc_parents_2),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -389,7 +389,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_pcie_1_aux_clk_src",

		.parent_data = gcc_parents_2,

		.num_parents = 3,

		.num_parents = ARRAY_SIZE(gcc_parents_2),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -410,7 +410,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_pcie_phy_refgen_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -432,7 +432,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_pdm2_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -455,7 +455,7 @@ static struct clk_rcg2 gcc_qspi_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qspi_core_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -489,7 +489,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s0_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -504,7 +504,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s1_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -519,7 +519,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s2_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -534,7 +534,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s3_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -549,7 +549,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s4_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -564,7 +564,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s5_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -579,7 +579,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s6_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -594,7 +594,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap0_s7_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -609,7 +609,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap1_s0_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -624,7 +624,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap1_s1_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -639,7 +639,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap1_s2_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -654,7 +654,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap1_s3_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -669,7 +669,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap1_s4_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -684,7 +684,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap1_s5_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -699,7 +699,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap2_s0_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -714,7 +714,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap2_s1_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -729,7 +729,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap2_s2_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -744,7 +744,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap2_s3_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -759,7 +759,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap2_s4_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -774,7 +774,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap2_s5_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -800,7 +800,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc2_apps_clk_src",

		.parent_data = gcc_parents_6,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parents_6),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_floor_ops,

	},
@@ -825,7 +825,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc4_apps_clk_src",

		.parent_data = gcc_parents_3,

		.num_parents = 3,

		.num_parents = ARRAY_SIZE(gcc_parents_3),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_floor_ops,

	},
@@ -845,7 +845,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_tsif_ref_clk_src",

		.parent_data = gcc_parents_7,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parents_7),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -869,7 +869,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_card_axi_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -892,7 +892,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_card_ice_core_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -912,7 +912,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_card_phy_aux_clk_src",

		.parent_data = gcc_parents_4,

		.num_parents = 2,

		.num_parents = ARRAY_SIZE(gcc_parents_4),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -934,7 +934,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_card_unipro_core_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -958,7 +958,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_axi_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -973,7 +973,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_ice_core_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -988,7 +988,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_phy_aux_clk_src",

		.parent_data = gcc_parents_4,

		.num_parents = 2,

		.num_parents = ARRAY_SIZE(gcc_parents_4),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -1003,7 +1003,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_unipro_core_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -1027,7 +1027,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb30_prim_master_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -1049,7 +1049,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb30_prim_mock_utmi_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -1064,7 +1064,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb30_sec_master_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -1079,7 +1079,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb30_sec_mock_utmi_clk_src",

		.parent_data = gcc_parents_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parents_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -1094,7 +1094,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb3_prim_phy_aux_clk_src",

		.parent_data = gcc_parents_2,

		.num_parents = 3,

		.num_parents = ARRAY_SIZE(gcc_parents_2),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},
@@ -1109,7 +1109,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb3_sec_phy_aux_clk_src",

		.parent_data = gcc_parents_2,

		.num_parents = 3,

		.num_parents = ARRAY_SIZE(gcc_parents_2),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},