Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 15ce1860 authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

msm: kgsl: Cleanup some of the a6xx gpudev functions 



Few functions can be handled directly without having
the gpuid checks. So cleanup these functions to avoid
unnecessary gpuid checks.

Change-Id: If5b88adb4d21d327a39dc92d657d1bf5066f6667
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 55572f84

drivers/gpu/msm/adreno.c

+0 −6
Original line number Diff line number Diff line
@@ -3062,9 +3062,6 @@ static void adreno_regwrite(struct kgsl_device *device, 
void adreno_read_gmu_wrapper(struct adreno_device *adreno_dev,

		u32 offsetwords, u32 *val)

{

	if (!adreno_dev->gmu_wrapper_virt)

		return;



	*val = __raw_readl(adreno_dev->gmu_wrapper_virt +

			(offsetwords << 2) - adreno_dev->gmu_wrapper_base);

	/* Order this read with respect to the following memory accesses */
@@ -3074,9 +3071,6 @@ void adreno_read_gmu_wrapper(struct adreno_device *adreno_dev, 
void adreno_write_gmu_wrapper(struct adreno_device *adreno_dev,

		u32 offsetwords, u32 value)

{

	if (!adreno_dev->gmu_wrapper_virt)

		return;



	/*

	 * ensure previous writes post before this one,

	 * i.e. act like normal writel()

drivers/gpu/msm/adreno_a6xx.c

+50 −55
Original line number Diff line number Diff line
@@ -109,25 +109,31 @@ static u32 a615_pwrup_reglist[] = { 


static int a6xx_get_cp_init_cmds(struct adreno_device *adreno_dev);



static void a6xx_gmu_wrapper_init(struct adreno_device *adreno_dev)

static int a6xx_gmu_wrapper_init(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct resource *res;



	if (adreno_dev->gmu_wrapper_virt)

		return;

		return 0;



	res = platform_get_resource_byname(device->pdev,

		IORESOURCE_MEM, "gmu_wrapper");

	if (!res)

		return;

	if (!res) {

		dev_err(device->dev, "gmu_wrapper platform_get_resource_byname failed\n");

		return -ENODEV;

	}



	adreno_dev->gmu_wrapper_base = res->start - device->reg_phys;

	adreno_dev->gmu_wrapper_virt = devm_ioremap(&device->pdev->dev,

		res->start, resource_size(res));



	if (!adreno_dev->gmu_wrapper_virt)

		dev_warn(device->dev, "gmu_wrapper ioremap failed\n");

	if (!adreno_dev->gmu_wrapper_virt) {

		dev_err(device->dev, "gmu_wrapper ioremap failed\n");

		return -ENODEV;

	}



	return 0;

}



static int match_name(struct device *dev, void *data)
@@ -164,7 +170,6 @@ int a6xx_init(struct adreno_device *adreno_dev) 
{

	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);



	a6xx_gmu_wrapper_init(adreno_dev);

	adreno_dev->highest_bank_bit = a6xx_core->highest_bank_bit;



	/* If the memory type is DDR 4, override the existing configuration */
@@ -193,6 +198,34 @@ int a6xx_init(struct adreno_device *adreno_dev) 
	return a6xx_get_cp_init_cmds(adreno_dev);

}



static int a6xx_holi_init(struct adreno_device *adreno_dev)

{

	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);

	int ret;



	ret = a6xx_gmu_wrapper_init(adreno_dev);

	if (ret)

		return ret;



	adreno_dev->highest_bank_bit = a6xx_core->highest_bank_bit;



	a6xx_crashdump_init(adreno_dev);



	if (IS_ERR_OR_NULL(adreno_dev->pwrup_reglist)) {

		adreno_dev->pwrup_reglist =

				kgsl_allocate_global(KGSL_DEVICE(adreno_dev),

					PAGE_SIZE, 0, 0, KGSL_MEMDESC_PRIVILEGED,

					"powerup_register_list");

		if (IS_ERR(adreno_dev->pwrup_reglist))

			return PTR_ERR(adreno_dev->pwrup_reglist);

	}



	find_ddr_qos_device(adreno_dev);



	return a6xx_get_cp_init_cmds(adreno_dev);

}





static void a6xx_protect_init(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -1171,38 +1204,6 @@ int a6xx_rb_start(struct adreno_device *adreno_dev) 
	return a6xx_post_start(adreno_dev);

}



/*

 * a6xx_sptprac_enable() - Power on SPTPRAC

 * @adreno_dev: Pointer to Adreno device

 */

static int a6xx_sptprac_enable(struct adreno_device *adreno_dev)

{

	return a6xx_gmu_sptprac_enable(adreno_dev);

}



/*

 * a6xx_sptprac_disable() - Power off SPTPRAC

 * @adreno_dev: Pointer to Adreno device

 */

static void a6xx_sptprac_disable(struct adreno_device *adreno_dev)

{

	a6xx_gmu_sptprac_disable(adreno_dev);

}



/*

 * a6xx_sptprac_is_on() - Check if SPTP is on using pwr status register

 * @adreno_dev - Pointer to adreno_device

 * This check should only be performed if the keepalive bit is set or it

 * can be guaranteed that the power state of the GPU will remain unchanged

 */

static bool a6xx_sptprac_is_on(struct adreno_device *adreno_dev)

{

	if (!adreno_has_sptprac_gdsc(adreno_dev))

		return true;



	return a6xx_gmu_sptprac_is_on(adreno_dev);

}



unsigned int a6xx_set_marker(

		unsigned int *cmds, enum adreno_cp_marker_type type)

{
@@ -2598,8 +2599,6 @@ const struct adreno_gpudev adreno_a6xx_gpudev = { 
	.init = a6xx_init,

	.irq_handler = a6xx_irq_handler,

	.rb_start = a6xx_rb_start,

	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.read_throttling_counters = a6xx_read_throttling_counters,

	.microcode_read = a6xx_microcode_read,

	.gpu_keepalive = a6xx_gpu_keepalive,
@@ -2612,7 +2611,6 @@ const struct adreno_gpudev adreno_a6xx_gpudev = { 
	.preemption_schedule = a6xx_preemption_schedule,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},
@@ -2650,8 +2648,8 @@ const struct adreno_gpudev adreno_a6xx_gmu_gpudev = { 
	.init = a6xx_init,

	.irq_handler = a6xx_irq_handler,

	.rb_start = a6xx_rb_start,

	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.regulator_enable = a6xx_gmu_sptprac_enable,

	.regulator_disable = a6xx_gmu_sptprac_disable,

	.read_throttling_counters = a6xx_read_throttling_counters,

	.microcode_read = a6xx_microcode_read,

	.gpu_keepalive = a6xx_gpu_keepalive,
@@ -2664,7 +2662,7 @@ const struct adreno_gpudev adreno_a6xx_gmu_gpudev = { 
	.preemption_schedule = a6xx_preemption_schedule,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.sptprac_is_on = a6xx_gmu_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},
@@ -2681,8 +2679,6 @@ const struct adreno_gpudev adreno_a6xx_rgmu_gpudev = { 
	.init = a6xx_init,

	.irq_handler = a6xx_irq_handler,

	.rb_start = a6xx_rb_start,

	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.read_throttling_counters = a6xx_read_throttling_counters,

	.microcode_read = a6xx_microcode_read,

	.gpu_keepalive = a6xx_gpu_keepalive,
@@ -2695,7 +2691,6 @@ const struct adreno_gpudev adreno_a6xx_rgmu_gpudev = { 
	.preemption_schedule = a6xx_preemption_schedule,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},
@@ -2709,11 +2704,11 @@ const struct adreno_gpudev adreno_a619_holi_gpudev = { 
	.probe = a6xx_probe,

	.start = a6xx_start,

	.snapshot = a6xx_snapshot,

	.init = a6xx_init,

	.init = a6xx_holi_init,

	.irq_handler = a6xx_irq_handler,

	.rb_start = a6xx_rb_start,

	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.regulator_enable = a6xx_holi_gmu_sptprac_enable,

	.regulator_disable = a6xx_holi_gmu_sptprac_disable,

	.read_throttling_counters = a6xx_read_throttling_counters,

	.microcode_read = a6xx_microcode_read,

	.gpu_keepalive = a6xx_gpu_keepalive,
@@ -2726,7 +2721,7 @@ const struct adreno_gpudev adreno_a619_holi_gpudev = { 
	.preemption_schedule = a6xx_preemption_schedule,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.sptprac_is_on = a6xx_holi_gmu_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},
@@ -2749,8 +2744,8 @@ const struct adreno_gpudev adreno_a630_gpudev = { 
	.init = a6xx_init,

	.irq_handler = a6xx_irq_handler,

	.rb_start = a6xx_rb_start,

	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.regulator_enable = a6xx_gmu_sptprac_enable,

	.regulator_disable = a6xx_gmu_sptprac_disable,

	.read_throttling_counters = a6xx_read_throttling_counters,

	.microcode_read = a6xx_microcode_read,

	.gpu_keepalive = a6xx_gpu_keepalive,
@@ -2763,7 +2758,7 @@ const struct adreno_gpudev adreno_a630_gpudev = { 
	.preemption_schedule = a6xx_preemption_schedule,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.sptprac_is_on = a6xx_gmu_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},

drivers/gpu/msm/adreno_a6xx.h

+6 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.

 */



#ifndef _ADRENO_A6XX_H_
@@ -315,7 +315,12 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 
void a6xx_crashdump_init(struct adreno_device *adreno_dev);

int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev);

void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev);

int a6xx_holi_gmu_sptprac_enable(struct adreno_device *adreno_dev);

void a6xx_holi_gmu_sptprac_disable(struct adreno_device *adreno_dev);



bool a6xx_gmu_sptprac_is_on(struct adreno_device *adreno_dev);

bool a6xx_holi_gmu_sptprac_is_on(struct adreno_device *adreno_dev);





/**

 * a6xx_read_alwayson - Read the current always on clock value

drivers/gpu/msm/adreno_a6xx_gmu.c

+68 −64
Original line number Diff line number Diff line
@@ -917,34 +917,7 @@ int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev) 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);



	if (adreno_is_a619_holi(adreno_dev)) {

		u32 val;

		void __iomem *addr = adreno_dev->gmu_wrapper_virt +

				(A6XX_GMU_SPTPRAC_PWR_CLK_STATUS << 2) -

				adreno_dev->gmu_wrapper_base;



		if (!adreno_dev->gmu_wrapper_virt) {

			dev_err(device->dev,

				"invalid gmu_wrapper addr, power on SPTPRAC fail\n");

			return -EINVAL;

		}



		adreno_write_gmu_wrapper(adreno_dev,

			A6XX_GMU_GX_SPTPRAC_POWER_CONTROL,

			SPTPRAC_POWERON_CTRL_MASK);



		if (readl_poll_timeout(addr, val,

			(val & SPTPRAC_POWERON_STATUS_MASK) ==

			SPTPRAC_POWERON_STATUS_MASK, 10,

			10 * 1000)) {

			dev_err(device->dev, "power on SPTPRAC fail\n");

			return -EINVAL;

		}

		return 0;

	}



	if (!gmu_core_gpmu_isenabled(device) ||

			!adreno_has_sptprac_gdsc(adreno_dev))

	if (!adreno_has_sptprac_gdsc(adreno_dev))

		return 0;



	gmu_core_regwrite(device, A6XX_GMU_GX_SPTPRAC_POWER_CONTROL,
@@ -964,45 +937,39 @@ int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev) 
}



/*

 * a6xx_gmu_sptprac_disable() - Power of SPTPRAC

 * a6xx_holi_gmu_sptprac_enable() - Power on SPTPRAC

 * @adreno_dev: Pointer to Adreno device

 */

void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev)

int a6xx_holi_gmu_sptprac_enable(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);



	if (adreno_is_a619_holi(adreno_dev)) {

	u32 val;

	void __iomem *addr = adreno_dev->gmu_wrapper_virt +

				(A6XX_GMU_SPTPRAC_PWR_CLK_STATUS << 2) -

				adreno_dev->gmu_wrapper_base;



		if (!adreno_dev->gmu_wrapper_virt) {

			dev_err(device->dev,

				"invalid gmu_wrapper addr, power off SPTPRAC fail\n");

			return;

	adreno_write_gmu_wrapper(adreno_dev, A6XX_GMU_GX_SPTPRAC_POWER_CONTROL,

		SPTPRAC_POWERON_CTRL_MASK);



	if (readl_poll_timeout(addr, val, (val & SPTPRAC_POWERON_STATUS_MASK) ==

		SPTPRAC_POWERON_STATUS_MASK, 10, 10 * 1000)) {

		dev_err(device->dev, "power on SPTPRAC fail\n");

		return -ETIMEDOUT;

	}



		/* Ensure that retention is on */

		adreno_read_gmu_wrapper(adreno_dev,

			A6XX_GPU_CC_GX_GDSCR, &val);

		adreno_write_gmu_wrapper(adreno_dev,

			A6XX_GPU_CC_GX_GDSCR,

			(val | A6XX_RETAIN_FF_ENABLE_ENABLE_MASK));

		adreno_write_gmu_wrapper(adreno_dev,

			A6XX_GMU_GX_SPTPRAC_POWER_CONTROL,

			SPTPRAC_POWEROFF_CTRL_MASK);

		if (readl_poll_timeout(addr, val,

			(val & SPTPRAC_POWEROFF_STATUS_MASK) ==

			SPTPRAC_POWEROFF_STATUS_MASK, 10,

			10 * 1000))

			dev_err(device->dev, "power off SPTPRAC fail\n");

		return;

	return 0;

}



	if (!gmu_core_gpmu_isenabled(device) ||

			!adreno_has_sptprac_gdsc(adreno_dev))

/*

 * a6xx_gmu_sptprac_disable() - Power of SPTPRAC

 * @adreno_dev: Pointer to Adreno device

 */

void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);



	if (!adreno_has_sptprac_gdsc(adreno_dev))

		return;



	/* Ensure that retention is on */
@@ -1020,6 +987,31 @@ void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev) 
		dev_err(&gmu->pdev->dev, "power off SPTPRAC fail\n");

}





/*

 * a6xx_holi_gmu_sptprac_disable() - Power of SPTPRAC

 * @adreno_dev: Pointer to Adreno device

 */

void a6xx_holi_gmu_sptprac_disable(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	u32 val;

	void __iomem *addr = adreno_dev->gmu_wrapper_virt +

			(A6XX_GMU_SPTPRAC_PWR_CLK_STATUS << 2) -

			adreno_dev->gmu_wrapper_base;



	/* Ensure that retention is on */

	adreno_read_gmu_wrapper(adreno_dev, A6XX_GPU_CC_GX_GDSCR, &val);

	adreno_write_gmu_wrapper(adreno_dev, A6XX_GPU_CC_GX_GDSCR,

		(val | A6XX_RETAIN_FF_ENABLE_ENABLE_MASK));

	adreno_write_gmu_wrapper(adreno_dev, A6XX_GMU_GX_SPTPRAC_POWER_CONTROL,

		SPTPRAC_POWEROFF_CTRL_MASK);



	if (readl_poll_timeout(addr, val, (val & SPTPRAC_POWEROFF_STATUS_MASK) ==

		SPTPRAC_POWEROFF_STATUS_MASK, 10, 10 * 1000))

		dev_err(device->dev, "power off SPTPRAC fail\n");

}



#define SPTPRAC_POWER_OFF	BIT(2)

#define SP_CLK_OFF		BIT(4)

#define GX_GDSC_POWER_OFF	BIT(6)
@@ -1045,14 +1037,26 @@ bool a6xx_gmu_sptprac_is_on(struct adreno_device *adreno_dev) 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	unsigned int val;



	if (gmu_core_isenabled(device))

	if (!adreno_has_sptprac_gdsc(adreno_dev))

		return true;



	gmu_core_regread(device, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS,

			&val);

	else if (adreno_is_a619_holi(adreno_dev))

		adreno_read_gmu_wrapper(adreno_dev,

			A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, &val);

	else

		return true;



	return !(val & (SPTPRAC_POWER_OFF | SP_CLK_OFF));

}



/*

 * a6xx_holi_gmu_sptprac_is_on() - Check if SPTP is on using pwr status register

 * @adreno_dev - Pointer to adreno_device

 * This check should only be performed if the keepalive bit is set or it

 * can be guaranteed that the power state of the GPU will remain unchanged

 */

bool a6xx_holi_gmu_sptprac_is_on(struct adreno_device *adreno_dev)

{

	unsigned int val;



	adreno_read_gmu_wrapper(adreno_dev, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, &val);



	return !(val & (SPTPRAC_POWER_OFF | SP_CLK_OFF));

}