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Commit 15b7dae0 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/psr: Update PSR2 SU corruption workaround comment 



Turn out it is not a DMC bug it is actually a HW one, so this
workaround will be needed for current gens, lets update the comment
and remove the FIXME.

BSpec: 7723
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190406005112.27205-1-jose.souza@intel.com
parent de220cc2

drivers/gpu/drm/i915/intel_psr.c

+2 −4
Original line number Original line Diff line number Diff line
@@ -534,10 +534,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
		val |= EDP_PSR2_TP2_TIME_2500us;

		val |= EDP_PSR2_TP2_TIME_2500us;





	/*

	/*

	 * FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin

	 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is

	 * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after

	 * recommending keep this bit unset while PSR2 is enabled.

	 * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now

	 * lets workaround the issue by cleaning PSR_CTL before enable PSR2.

	 */

	 */

	I915_WRITE(EDP_PSR_CTL, 0);

	I915_WRITE(EDP_PSR_CTL, 0);