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Commit 152a9e1a authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Remove "zero" power level 



There was a time, long long ago, when having a "zero" power level made
sense because a "zero" powerlevel wasn't really "zero". That is no longer
the case and it is silly to force the DT to define it for EVERY. SINGLE.
TARGET. Get rid of it and assume that zero is, well... zero.

Change-Id: Ic0dedbadc5551585de893cdb5b3ed948a62aa430
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 186835c7

drivers/gpu/msm/adreno.c

+17 −9
Original line number Diff line number Diff line
@@ -842,7 +842,7 @@ static void adreno_of_get_ca_target_pwrlevel(struct adreno_device *adreno_dev, 
	of_property_read_u32(node, "qcom,ca-target-pwrlevel",

		&ca_target_pwrlevel);



	if (ca_target_pwrlevel > device->pwrctrl.num_pwrlevels - 2)

	if (ca_target_pwrlevel >= device->pwrctrl.num_pwrlevels)

		ca_target_pwrlevel = 1;



	device->pwrscale.ctxt_aware_target_pwrlevel = ca_target_pwrlevel;
@@ -907,15 +907,27 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, 
	pwr->num_pwrlevels = 0;



	for_each_child_of_node(node, child) {

		unsigned int index;

		unsigned int index, freq = 0;

		struct kgsl_pwrlevel *level;



		if (of_property_read_u32(child, "reg", &index)) {

			dev_err(device->dev,

				"%pOF: powerlevel index not found\n", child);

			of_node_put(child);

			return -EINVAL;

		}



		if (of_property_read_u32(child, "qcom,gpu-freq", &freq)) {

			dev_err(device->dev,

				"%pOF: Unable to read qcom,gpu-freq\n", child);

			of_node_put(child);

			return -EINVAL;

		}



		/* Ignore "zero" powerlevels */

		if (!freq)

			continue;



		if (index >= KGSL_MAX_PWRLEVELS) {

			dev_err(device->dev,

				"%pOF: Pwrlevel index %d is out of range\n",
@@ -928,12 +940,7 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, 


		level = &pwr->pwrlevels[index];



		if (of_property_read_u32(child, "qcom,gpu-freq",

			&level->gpu_freq)) {

			dev_err(device->dev,

				"%pOF: Unable to read qcom,gpu-freq\n", child);

			return -EINVAL;

		}

		level->gpu_freq = freq;



		of_property_read_u32(child, "qcom,acd-level",

			&level->acd_level);
@@ -944,6 +951,7 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, 
			dev_err(device->dev,

				"%pOF: Couldn't read the bus frequency for power level %d\n",

				child, index);

			of_node_put(child);

			return ret;

		}
@@ -968,7 +976,7 @@ static void adreno_of_get_initial_pwrlevel(struct adreno_device *adreno_dev, 


	of_property_read_u32(node, "qcom,initial-pwrlevel", &init_level);



	if (init_level < 0 || init_level > pwr->num_pwrlevels)

	if (init_level < 0 || init_level >= pwr->num_pwrlevels)

		init_level = 1;



	pwr->active_pwrlevel = init_level;

drivers/gpu/msm/adreno_a5xx.c

+3 −4
Original line number Diff line number Diff line
@@ -934,14 +934,13 @@ static uint32_t _write_voltage_table(struct adreno_device *adreno_dev, 
	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);

	int i;

	struct dev_pm_opp *opp;

	int levels = pwr->num_pwrlevels - 1;

	unsigned int mvolt = 0;



	kgsl_regwrite(device, addr++, a5xx_core->max_power);

	kgsl_regwrite(device, addr++, levels);

	kgsl_regwrite(device, addr++, pwr->num_pwrlevels);



	/* Write voltage in mV and frequency in MHz */

	for (i = 0; i < levels; i++) {

	for (i = 0; i < pwr->num_pwrlevels; i++) {

		opp = dev_pm_opp_find_freq_exact(&device->pdev->dev,

				pwr->pwrlevels[i].gpu_freq, true);

		/* _opp_get returns uV, convert to mV */
@@ -953,7 +952,7 @@ static uint32_t _write_voltage_table(struct adreno_device *adreno_dev, 
		kgsl_regwrite(device, addr++,

				pwr->pwrlevels[i].gpu_freq / 1000000);

	}

	return (levels * 2 + 2);

	return (pwr->num_pwrlevels * 2 + 2);

}



static uint32_t lm_limit(struct adreno_device *adreno_dev)

drivers/gpu/msm/adreno_a6xx_gmu.c

+2 −1
Original line number Diff line number Diff line
@@ -830,7 +830,8 @@ static int a6xx_gmu_gfx_rail_on(struct kgsl_device *device) 
{

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);

	unsigned int perf_idx = pwr->num_pwrlevels - pwr->default_pwrlevel - 1;

	unsigned int perf_idx = gmu->num_gpupwrlevels -

		pwr->default_pwrlevel - 1;

	uint32_t default_opp = gmu->rpmh_votes.gx_votes[perf_idx];



	gmu_core_regwrite(device, A6XX_GMU_BOOT_SLUMBER_OPTION,

drivers/gpu/msm/kgsl_gmu.c

+9 −8
Original line number Diff line number Diff line
@@ -486,7 +486,7 @@ static int gmu_memory_probe(struct kgsl_device *device) 
 * to index being used by GMU/RPMh.

 */

static int gmu_dcvs_set(struct kgsl_device *device,

		unsigned int gpu_pwrlevel, unsigned int bus_level)

		int gpu_pwrlevel, int bus_level)

{

	int ret = 0;

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);
@@ -1193,7 +1193,7 @@ static void gmu_acd_probe(struct kgsl_device *device, struct gmu_device *gmu, 
	cmd->enable_by_level = 0;



	for (i = 0, cmd_idx = 0; i < numlvl; i++) {

		acd_level = pwr->pwrlevels[numlvl - i - 1].acd_level;

		acd_level = pwr->pwrlevels[numlvl - i].acd_level;

		if (acd_level) {

			cmd->enable_by_level |= (1 << i);

			cmd->data[cmd_idx++] = acd_level;
@@ -1218,7 +1218,7 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node) 
	struct kgsl_hfi *hfi;

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	int i = 0, ret = -ENXIO;

	int i = 0, ret = -ENXIO, index = 0;



	gmu = kzalloc(sizeof(struct gmu_device), GFP_KERNEL);
@@ -1288,13 +1288,14 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node) 
	tasklet_init(&hfi->tasklet, hfi_receiver, (unsigned long) gmu);

	hfi->kgsldev = device;



	gmu->num_gpupwrlevels = pwr->num_pwrlevels;

	/* Add a dummy level for "off" that the GMU expects */

	gmu->gpu_freqs[index++] = 0;



	for (i = 0; i < gmu->num_gpupwrlevels; i++) {

		int j = gmu->num_gpupwrlevels - 1 - i;

	/* GMU power levels are in ascending order */

	for (i = pwr->num_pwrlevels - 1; i >= 0; i--)

		gmu->gpu_freqs[index++] = pwr->pwrlevels[i].gpu_freq;



		gmu->gpu_freqs[i] = pwr->pwrlevels[j].gpu_freq;

	}

	gmu->num_gpupwrlevels = pwr->num_pwrlevels + 1;



	gmu->icc_path = of_icc_get(&gmu->pdev->dev, NULL);

drivers/gpu/msm/kgsl_gmu_core.c

+2 −2
Original line number Diff line number Diff line
@@ -153,8 +153,8 @@ void gmu_core_snapshot(struct kgsl_device *device) 
		gmu_core_ops->snapshot(device);

}



int gmu_core_dcvs_set(struct kgsl_device *device, unsigned int gpu_pwrlevel,

		unsigned int bus_level)

int gmu_core_dcvs_set(struct kgsl_device *device, int gpu_pwrlevel,

		int bus_level)

{

	struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device);