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Commit 151481ef authored by Vidya Sagar's avatar Vidya Sagar Committed by Lorenzo Pieralisi
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dt-bindings: PCI: tegra: Add sideband pins configuration entries 



Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin
configuration information of a particular PCIe controller.

Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarAndrew Murray <andrew.murray@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
parent 56e15a23

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt

+8 −0
Original line number Diff line number Diff line
@@ -83,6 +83,11 @@ Required properties: 
- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals



Optional properties:

- pinctrl-names: A list of pinctrl state names.

  It is mandatory for C5 controller and optional for other controllers.

  - "default": Configures PCIe I/O for proper operation.

- pinctrl-0: phandle for the 'default' state of pin configuration.

  It is mandatory for C5 controller and optional for other controllers.

- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt

- nvidia,update-fc-fixup: This is a boolean property and needs to be present to

    improve performance when a platform is designed in such a way that it
@@ -120,6 +125,9 @@ Tegra194: 
		num-lanes = <8>;

		linux,pci-domain = <0>;



		pinctrl-names = "default";

		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;



		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;

		clock-names = "core";