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Commit 1510d5b8 authored by Dharmender Sharma's avatar Dharmender Sharma Committed by Gerrit - the friendly Code Review server
Browse files

msm: camera: jpeg: JPEG HW and Camnoc MISR 



Support for Camnoc MISR for JPEG DMA and Encoder.
Also added support for seprate target files.

CRs-Fixed: 3012752
Change-Id: I5e066d5d871f58073f669c01270d5b64ce16088e
Signed-off-by: default avatarDharmender Sharma <dharshar@codeaurora.org>
Signed-off-by: default avatarShravya Samala <shravyas@codeaurora.org>
parent 8ef61574

drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c

+82 −4
Original line number Diff line number Diff line
@@ -142,6 +142,13 @@ static int cam_jpeg_process_next_hw_update(void *priv, void *data, 


	CAM_TRACE(CAM_JPEG, "Start JPEG ENC Req %llu", config_args->request_id);



	/* configure jpeg hw and camnoc misr */

	rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd(

		hw_mgr->devices[dev_type][0]->hw_priv,

		CAM_JPEG_CMD_CONFIG_HW_MISR,

		&g_jpeg_hw_mgr.camnoc_misr_test,

		sizeof(g_jpeg_hw_mgr.camnoc_misr_test));



	rc = hw_mgr->devices[dev_type][0]->hw_ops.start(

		hw_mgr->devices[dev_type][0]->hw_priv, NULL, 0);

	if (rc) {
@@ -174,6 +181,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) 
	struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL;

	struct crm_workq_task *task;

	struct cam_jpeg_process_frame_work_data_t *wq_task_data;

	struct cam_jpeg_misr_dump_args misr_args;



	if (!data || !priv) {

		CAM_ERR(CAM_JPEG, "Invalid data");
@@ -203,8 +211,19 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) 
	}



	p_cfg_req->num_hw_entry_processed++;

	CAM_DBG(CAM_JPEG, "hw entry processed %d",

		p_cfg_req->num_hw_entry_processed);

	CAM_DBG(CAM_JPEG, "hw entry processed %d Encoded size :%d",

		p_cfg_req->num_hw_entry_processed, task_data->result_size);



	misr_args.req_id = p_cfg_req->req_id;

	misr_args.enable_bug = g_jpeg_hw_mgr.bug_on_misr;

	CAM_DBG(CAM_JPEG, "req %lld bug is enabled for MISR :%d",

		misr_args.req_id, misr_args.enable_bug);



	/* dump jpeg hw and camnoc misr */

	rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd(

		hw_mgr->devices[dev_type][0]->hw_priv,

		CAM_JPEG_CMD_DUMP_HW_MISR_VAL, &misr_args,

		sizeof(struct cam_jpeg_misr_dump_args));



	if ((task_data->result_size > 0) &&

		(p_cfg_req->num_hw_entry_processed <
@@ -298,7 +317,6 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) 
	p_params = (struct cam_jpeg_config_inout_param_info *)cmd_buf_kaddr;



	p_params->output_size = task_data->result_size;

	CAM_DBG(CAM_JPEG, "Encoded Size %d", task_data->result_size);



	buf_data.num_handles =

		p_cfg_req->hw_cfg_args.num_out_map_entries;
@@ -1791,6 +1809,64 @@ static int cam_jpeg_mgr_cmd(void *hw_mgr_priv, void *cmd_args) 
	return rc;

}



static int cam_jpeg_set_camnoc_misr_test(void *data, u64 val)

{

	g_jpeg_hw_mgr.camnoc_misr_test = val;

	return 0;

}



static int cam_jpeg_get_camnoc_misr_test(void *data, u64 *val)

{

	*val = g_jpeg_hw_mgr.camnoc_misr_test;

	return 0;

}

DEFINE_DEBUGFS_ATTRIBUTE(camnoc_misr_test, cam_jpeg_get_camnoc_misr_test,

	cam_jpeg_set_camnoc_misr_test, "%08llu");



static int cam_jpeg_set_bug_on_misr(void *data, u64 val)

{

	g_jpeg_hw_mgr.bug_on_misr = val;

	return 0;

}



static int cam_jpeg_get_bug_on_misr(void *data, u64 *val)

{

	*val = g_jpeg_hw_mgr.bug_on_misr;

	return 0;

}

DEFINE_DEBUGFS_ATTRIBUTE(bug_on_misr_mismatch, cam_jpeg_get_bug_on_misr,

	cam_jpeg_set_bug_on_misr, "%08llu");



static int cam_jpeg_mgr_create_debugfs_entry(void)

{

	int rc = 0;

	struct dentry *dbgfileptr = NULL;



	dbgfileptr = debugfs_create_dir("camera_jpeg", NULL);

	if (!dbgfileptr) {

		CAM_ERR(CAM_JPEG, "DebugFS could not create directory!");

		rc = -ENOENT;

		goto err;

	}

	/* Store parent inode for cleanup in caller */

	g_jpeg_hw_mgr.dentry = dbgfileptr;



	dbgfileptr = debugfs_create_file("camnoc_misr_test", 0644,

		g_jpeg_hw_mgr.dentry, NULL, &camnoc_misr_test);



	dbgfileptr = debugfs_create_file("bug_on_misr_mismatch", 0644,

		g_jpeg_hw_mgr.dentry, NULL, &bug_on_misr_mismatch);



	if (IS_ERR(dbgfileptr)) {

		if (PTR_ERR(dbgfileptr) == -ENODEV)

			CAM_WARN(CAM_JPEG, "DebugFS not enabled in kernel!");

		else

			rc = PTR_ERR(dbgfileptr);

	}

err:

	return rc;

}



int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl,

	int *iommu_hdl)

{
@@ -1877,6 +1953,8 @@ int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, 
	if (iommu_hdl)

		*iommu_hdl = g_jpeg_hw_mgr.iommu_hdl;



	rc = cam_jpeg_mgr_create_debugfs_entry();

	if (!rc)

		return rc;



cdm_iommu_failed:

drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h

+6 −0
Original line number Diff line number Diff line
@@ -124,6 +124,9 @@ struct cam_jpeg_hw_ctx_data { 
 * @process_irq_cb_work_data: Work data pool for irq requests

 * @cdm_iommu_hdl: Iommu handle received from cdm

 * @cdm_iommu_hdl_secure: Secure iommu handle received from cdm

 * @dentry: Debugfs entry

 * @camnoc_misr_test : debugfs entry to select camnoc_misr for read or write path

 * @bug_on_misr : enable/disable bug on when misr mismatch is seen

 * @devices: Core hw Devices of JPEG hardware manager

 * @cdm_info: Cdm info for each core device.

 * @cdm_reg_map: Regmap of each device for cdm.
@@ -147,6 +150,9 @@ struct cam_jpeg_hw_mgr { 
	struct cam_jpeg_process_irq_work_data_t *process_irq_cb_work_data;

	int cdm_iommu_hdl;

	int cdm_iommu_hdl_secure;

	struct dentry *dentry;

	u64 camnoc_misr_test;

	u64 bug_on_misr;



	struct cam_hw_intf **devices[CAM_JPEG_DEV_TYPE_MAX];

	struct cam_jpeg_hw_cdm_info_t cdm_info[CAM_JPEG_DEV_TYPE_MAX]

drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h

+18 −0
Original line number Diff line number Diff line
@@ -18,6 +18,11 @@ 
#define CAM_JPEG_HW_DUMP_TAG_MAX_LEN 32

#define CAM_JPEG_HW_DUMP_NUM_WORDS   5

#define CAM_JPEG_HW_MAX_NUM_PID      2

#define CAM_JPEG_CAMNOC_MISR_VAL_ROW 2

#define CAM_JPEG_CAMNOC_MISR_VAL_COL 4

#define CAM_JPEG_ENC_MISR_VAL_NUM    3

#define CAM_JPEG_MISR_ID_LOW_RD      0

#define CAM_JPEG_MISR_ID_LOW_WR      1



enum cam_jpeg_hw_type {

	CAM_JPEG_DEV_ENC,
@@ -51,12 +56,25 @@ struct cam_jpeg_match_pid_args { 
	uint32_t    match_res;

};



/**

 * struct cam_jpeg_misr_dump_args

 * @req_id: Request Id

 * @enable_bug: This flag indicates whether BUG_ON(1) has to be called or not

 * on MISR mismatch

 */

struct cam_jpeg_misr_dump_args {

	uint32_t    req_id;

	bool        enable_bug;

};



enum cam_jpeg_cmd_type {

	CAM_JPEG_CMD_CDM_CFG,

	CAM_JPEG_CMD_SET_IRQ_CB,

	CAM_JPEG_CMD_HW_DUMP,

	CAM_JPEG_CMD_GET_NUM_PID,

	CAM_JPEG_CMD_MATCH_PID_MID,

	CAM_JPEG_CMD_CONFIG_HW_MISR,

	CAM_JPEG_CMD_DUMP_HW_MISR_VAL,

	CAM_JPEG_CMD_MAX,

};

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_165_hw_info_ver_4_2_0.h

0 → 100644
+75 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 */



#ifndef CAM_JPEG_DMA_165_HW_INFO_VER_4_2_0_H

#define CAM_JPEG_DMA_165_HW_INFO_VER_4_2_0_H



#define CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE (1 << 0)

#define CAM_JPEGDMA_HW_IRQ_STATUS_RD_BUF_DONE  (1 << 1)

#define CAM_JPEGDMA_HW_IRQ_STATUS_WR_BUF_DONE  (1 << 5)

#define CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT     (1 << 9)

#define CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE     (1 << 10)



#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1



#define CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE \

		CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE

#define CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK \

		CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE



static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_165_hw_info = {

	.reg_offset = {

		.hw_version = 0x0,

		.int_clr = 0x14,

		.int_status = 0x10,

		.int_mask = 0x0C,

		.hw_cmd = 0x1C,

		.reset_cmd = 0x08,

		.encode_size = 0x180,

		.core_cfg = 0x18,

		.misr_cfg0 = 0x160,

		.misr_cfg1 = 0x164,

	},

	.reg_val = {

		.int_clr_clearall = 0xFFFFFFFF,

		.int_mask_disable_all = 0x00000000,

		.int_mask_enable_all = 0xFFFFFFFF,

		.hw_cmd_start = 0x00000001,

		.reset_cmd = 0x32083,

		.hw_cmd_stop = 0x00000004,

		.misr_cfg0 = 0x506,

	},

	.int_status = {

		.framedone = CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE,

		.resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK,

		.iserror = 0x0,

		.stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT,

		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,

		.scale_enable_shift = 0x4,

	},

	.camnoc_misr_reg_offset = {

		.main_ctl = 0x5908,

		.id_mask_low = 0x5920,

		.id_value_low = 0x5918,

		.misc_ctl = 0x5910,

		.sigdata0 = 0x5950,

	},

	.camnoc_misr_reg_val = {

		.main_ctl = 0x7,

		.id_mask_low = 0xFC0,

		.id_value_low_rd = 0xD00,

		.id_value_low_wr = 0xD42,

		.misc_ctl_start = 0x1,

		.misc_ctl_stop = 0x2,

	},

	.max_misr = 3,

	.max_misr_rd = 4,

	.max_misr_wr = 4,

	.camnoc_misr_sigdata = 4,

	.master_we_sel = 2,

	.misr_rd_word_sel = 4,

};



#endif /* CAM_JPEG_DMA_165_HW_INFO_VER_4_2_0_H */

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_580_hw_info_ver_4_2_0.h

0 → 100644
+75 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 */



#ifndef CAM_JPEG_DMA_580_HW_INFO_VER_4_2_0_H

#define CAM_JPEG_DMA_580_HW_INFO_VER_4_2_0_H



#define CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE (1 << 0)

#define CAM_JPEGDMA_HW_IRQ_STATUS_RD_BUF_DONE  (1 << 1)

#define CAM_JPEGDMA_HW_IRQ_STATUS_WR_BUF_DONE  (1 << 5)

#define CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT     (1 << 9)

#define CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE     (1 << 10)



#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1



#define CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE \

		CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE

#define CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK \

		CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE



static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_580_hw_info = {

	.reg_offset = {

		.hw_version = 0x0,

		.int_clr = 0x14,

		.int_status = 0x10,

		.int_mask = 0x0C,

		.hw_cmd = 0x1C,

		.reset_cmd = 0x08,

		.encode_size = 0x180,

		.core_cfg = 0x18,

		.misr_cfg0 = 0x160,

		.misr_cfg1 = 0x164,

	},

	.reg_val = {

		.int_clr_clearall = 0xFFFFFFFF,

		.int_mask_disable_all = 0x00000000,

		.int_mask_enable_all = 0xFFFFFFFF,

		.hw_cmd_start = 0x00000001,

		.reset_cmd = 0x32083,

		.hw_cmd_stop = 0x00000004,

		.misr_cfg0 = 0x506,

	},

	.int_status = {

		.framedone = CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE,

		.resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK,

		.iserror = 0x0,

		.stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT,

		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,

		.scale_enable_shift = 0x4,

	},

	.camnoc_misr_reg_offset = {

		.main_ctl = 0x3608,

		.id_mask_low = 0x3620,

		.id_value_low = 0x3618,

		.misc_ctl = 0x3610,

		.sigdata0 = 0x3650,

	},

	.camnoc_misr_reg_val = {

		.main_ctl = 0x7,

		.id_mask_low = 0xFC0,

		.id_value_low_rd = 0xD00,

		.id_value_low_wr = 0xD42,

		.misc_ctl_start = 0x1,

		.misc_ctl_stop = 0x2,

	},

	.max_misr = 3,

	.max_misr_rd = 4,

	.max_misr_wr = 4,

	.camnoc_misr_sigdata = 4,

	.master_we_sel = 2,

	.misr_rd_word_sel = 4,

};



#endif /* CAM_JPEG_DMA_580_HW_INFO_VER_4_2_0_H */