Merge branch 'spi-5.1' into spi-next

* Atmel Quad Serial Peripheral Interface (QSPI)

Required properties:

- compatible:     Should be "atmel,sama5d2-qspi".

- compatible:     Should be one of the following:

		  - "atmel,sama5d2-qspi"

		  - "microchip,sam9x60-qspi"

- reg:            Should contain the locations and lengths of the base registers

                  and the mapped memory.

- reg-names:      Should contain the resource reg names:

                  - qspi_base: configuration register address space

                  - qspi_mmap: memory mapped address space

- interrupts:     Should contain the interrupt for the device.

- clocks:         The phandle of the clock needed by the QSPI controller.

- clocks:         Should reference the peripheral clock and the QSPI system

                  clock if available.

- clock-names:    Should contain "pclk" for the peripheral clock and "qspick"

                  for the system clock when available.

- #address-cells: Should be <1>.

- #size-cells:    Should be <0>.

	reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;

	reg-names = "qspi_base", "qspi_mmap";

	interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;

	clocks = <&spi0_clk>;

	clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;

	clock-names = "pclk";

	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-names = "default";

  - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35

  - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51

  - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc

  - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M

- reg : Offset and length of the register set for the device

- interrupts : Should contain CSPI/eCSPI interrupt

- clocks : Clock specifiers for both ipg and per clocks.

  - clocks : The clocks needed by the QuadSPI controller

  - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".

Optional properties:

  - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.

                              Each bus can be connected with two NOR flashes.

			      Most of the time, each bus only has one NOR flash

			      connected, this is the default case.

			      But if there are two NOR flashes connected to the

			      bus, you should enable this property.

			      (Please check the board's schematic.)

  - big-endian : That means the IP register is big endian

Required SPI slave node properties:

  - reg: There are two buses (A and B) with two chip selects each.

	 This encodes to which bus and CS the flash is connected:

		<0>: Bus A, CS 0

		<1>: Bus A, CS 1

		<2>: Bus B, CS 0

		<3>: Bus B, CS 1

Example:

	};

};

Example showing the usage of two SPI NOR devices:

Example showing the usage of two SPI NOR devices on bus A:

&qspi2 {

	pinctrl-names = "default";

* NXP Flex Serial Peripheral Interface (FSPI)

Required properties:

  - compatible : Should be "nxp,lx2160a-fspi"

  - reg :        First contains the register location and length,

                 Second contains the memory mapping address and length

  - reg-names :  Should contain the resource reg names:

	         - fspi_base: configuration register address space

                 - fspi_mmap: memory mapped address space

  - interrupts : Should contain the interrupt for the device

Required SPI slave node properties:

  - reg :        There are two buses (A and B) with two chip selects each.

                 This encodes to which bus and CS the flash is connected:

                 - <0>: Bus A, CS 0

                 - <1>: Bus A, CS 1

                 - <2>: Bus B, CS 0

                 - <3>: Bus B, CS 1

Example showing the usage of two SPI NOR slave devices on bus A:

fspi0: spi@20c0000 {

	compatible = "nxp,lx2160a-fspi";

	reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>;

	reg-names = "fspi_base", "fspi_mmap";

	interrupts = <0 25 0x4>; /* Level high type */

	clocks = <&clockgen 4 3>, <&clockgen 4 3>;

	clock-names = "fspi_en", "fspi";

	mt35xu512aba0: flash@0 {

		reg = <0>;

		....

	};

	mt35xu512aba1: flash@1 {

		reg = <1>;

		....

	};

};

SiFive SPI controller Device Tree Bindings

------------------------------------------

Required properties:

- compatible		: Should be "sifive,<chip>-spi" and "sifive,spi<version>".

			  Supported compatible strings are:

			  "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated

			  onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive

			  SPI v0 IP block with no chip integration tweaks.

			  Please refer to sifive-blocks-ip-versioning.txt for details

- reg			: Physical base address and size of SPI registers map

			  A second (optional) range can indicate memory mapped flash

- interrupts		: Must contain one entry

- interrupt-parent	: Must be core interrupt controller

- clocks		: Must reference the frequency given to the controller

- #address-cells	: Must be '1', indicating which CS to use

- #size-cells		: Must be '0'

Optional properties:

- sifive,fifo-depth		: Depth of hardware queues; defaults to 8

- sifive,max-bits-per-word	: Maximum bits per word; defaults to 8

SPI RTL that corresponds to the IP block version numbers can be found here:

https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi

Example:

	spi: spi@10040000 {

		compatible = "sifive,fu540-c000-spi", "sifive,spi0";

		reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;

		interrupt-parent = <&plic>;

		interrupts = <51>;

		clocks = <&tlclk>;

		#address-cells = <1>;

		#size-cells = <0>;

		sifive,fifo-depth = <8>;

		sifive,max-bits-per-word = <8>;

	};