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Commit 14bd7f0a authored by Mayank Rana's avatar Mayank Rana
Browse files

Revert "dwc3-msm: Add support to vote USB FORCE_MEM_CORE_ON" 



This change reverts commit ("f1984dce dwc3-msm: Add support to vote
USB FORCE_MEM_CORE_ON") which is using dummy clock to update USB
master clock for keeping USB controller CSR retain while going into
CXPC. There is new API qcom_clk_set_flags() propose which supports
same functionality without USB dummy clock.

Change-Id: I0e35e4dac265a22eac2c3e95946cc9171c309508
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent 99e8c416

drivers/usb/dwc3/dwc3-msm.c

+0 −12
Original line number Diff line number Diff line
@@ -401,7 +401,6 @@ struct dwc3_msm { 
	struct list_head req_complete_list;

	struct clk		*xo_clk;

	struct clk		*core_clk;

	struct clk		*core_csr_clk;

	long			core_clk_rate;

	long			core_clk_rate_hs;

	struct clk		*iface_clk;
@@ -2189,15 +2188,8 @@ static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) 
		}



		qcom_clk_set_flags(mdwc->core_clk, CLKFLAG_RETAIN_MEM);

		ret = clk_prepare_enable(mdwc->core_csr_clk);

		if (ret) {

			regulator_disable(mdwc->dwc3_gdsc);

			dev_err(mdwc->dev, "unable to enable core_csr_clks\n");

			return ret;

		}

	} else {

		qcom_clk_set_flags(mdwc->core_clk, CLKFLAG_NORETAIN_MEM);

		clk_disable_unprepare(mdwc->core_csr_clk);

		ret = regulator_disable(mdwc->dwc3_gdsc);

		if (ret) {

			dev_err(mdwc->dev, "unable to disable usb3 gdsc\n");
@@ -3459,10 +3451,6 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) 
		return ret;

	}



	mdwc->core_csr_clk = devm_clk_get(mdwc->dev, "core_csr_clk");

	if (IS_ERR(mdwc->core_csr_clk))

		mdwc->core_csr_clk = NULL;



	mdwc->core_reset = devm_reset_control_get(mdwc->dev, "core_reset");

	if (IS_ERR(mdwc->core_reset)) {

		dev_err(mdwc->dev, "failed to get core_reset\n");