Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 13fdae1a authored by Bai Ping's avatar Bai Ping Committed by Shawn Guo
Browse files

ARM: dts: imx: Fix the assigned-clock mismatch issue on imx6q/dl 



The 'assigned-clock-parents' and 'assigned-clock-rates' list
should corresponding to the 'assigned-clocks' property clock list.

Signed-off-by: default avatarBai Ping <b51503@freescale.com>
Fixes: ed339363 ("ARM: dts: imx6qdl-sabreauto: Allow HDMI and LVDS to work simultaneously")
Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 9c171905

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -113,14 +113,14 @@ 
&clks {

	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,

			  <&clks IMX6QDL_PLL4_BYPASS>,

			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>,

			  <&clks IMX6QDL_CLK_LDB_DI0_SEL>,

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,

			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,

				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,

				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,

				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

	assigned-clock-rates = <0>, <0>, <24576000>;

	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;

};



&ecspi1 {