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Commit 13e53c5c authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Chris Wilson
Browse files

drm/i915/tgl: Introduce initial Tiger Lake workarounds 



Add empty workaround hooks for Tiger Lake. The workarounds will be added
on separate patches. We were already applying
WaRsForcewakeAddDelayForAck, which is indeed still valid, so also update
the comment.

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190817093902.2171-21-lucas.demarchi@intel.com
parent f4785682

drivers/gpu/drm/i915/gt/intel_lrc.c

+1 −0
Original line number Diff line number Diff line
@@ -2225,6 +2225,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) 
		return 0;



	switch (INTEL_GEN(engine->i915)) {

	case 12:

	case 11:

		return 0;

	case 10:

drivers/gpu/drm/i915/gt/intel_workarounds.c

+23 −3
Original line number Diff line number Diff line
@@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 
			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);

}



static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,

				     struct i915_wa_list *wal)

{

}



static void

__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,

			   struct i915_wa_list *wal,
@@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 


	wa_init_start(wal, name, engine->name);



	if (IS_GEN(i915, 11))

	if (IS_GEN(i915, 12))

		tgl_ctx_workarounds_init(engine, wal);

	else if (IS_GEN(i915, 11))

		icl_ctx_workarounds_init(engine, wal);

	else if (IS_CANNONLAKE(i915))

		cnl_ctx_workarounds_init(engine, wal);
@@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		    GAMT_CHKN_DISABLE_L3_COH_PIPE);

}



static void

tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{

}



static void

gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)

{

	if (IS_GEN(i915, 11))

	if (IS_GEN(i915, 12))

		tgl_gt_workarounds_init(i915, wal);

	else if (IS_GEN(i915, 11))

		icl_gt_workarounds_init(i915, wal);

	else if (IS_CANNONLAKE(i915))

		cnl_gt_workarounds_init(i915, wal);
@@ -1183,6 +1197,10 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) 
	}

}



static void tgl_whitelist_build(struct intel_engine_cs *engine)

{

}



void intel_engine_init_whitelist(struct intel_engine_cs *engine)

{

	struct drm_i915_private *i915 = engine->i915;
@@ -1190,7 +1208,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) 


	wa_init_start(w, "whitelist", engine->name);



	if (IS_GEN(i915, 11))

	if (IS_GEN(i915, 12))

		tgl_whitelist_build(engine);

	else if (IS_GEN(i915, 11))

		icl_whitelist_build(engine);

	else if (IS_CANNONLAKE(i915))

		cnl_whitelist_build(engine);

drivers/gpu/drm/i915/intel_pm.c

+3 −1
Original line number Diff line number Diff line
@@ -9597,7 +9597,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) 
 */

void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)

{

	if (IS_GEN(dev_priv, 11))

	if (IS_GEN(dev_priv, 12))

		dev_priv->display.init_clock_gating = nop_init_clock_gating;

	else if (IS_GEN(dev_priv, 11))

		dev_priv->display.init_clock_gating = icl_init_clock_gating;

	else if (IS_CANNONLAKE(dev_priv))

		dev_priv->display.init_clock_gating = cnl_init_clock_gating;