Merge "msm: gsi: gsi 2.9 upgrade" (13db81d1) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/platform/msm/gsi/gsi.c

+18 −0

Original line number	Diff line number	Diff line
		@@ -867,6 +867,13 @@ static uint32_t gsi_get_max_channels(enum gsi_ver ver)
		GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK) >>
		GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT;
		break;
		case GSI_VER_2_9:
		reg = gsi_readl(gsi_ctx->base +
		GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(gsi_ctx->per.ee));
		reg = (reg &
		GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK) >>
		GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT;
		break;
		}

		GSIDBG("max channels %d\n", reg);
		@@ -931,6 +938,13 @@ static uint32_t gsi_get_max_event_rings(enum gsi_ver ver)
		GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK) >>
		GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT;
		break;
		case GSI_VER_2_9:
		reg = gsi_readl(gsi_ctx->base +
		GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(gsi_ctx->per.ee));
		reg = (reg &
		GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK) >>
		GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT;
		break;
		}

		GSIDBG("max event rings %d\n", reg);
		@@ -1056,6 +1070,7 @@ int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)
		break;
		case GSI_VER_2_5:
		case GSI_VER_2_7:
		case GSI_VER_2_9:
		needed_reg_ver = GSI_REGISTER_VER_2;
		break;
		case GSI_VER_ERR:
		@@ -4078,6 +4093,9 @@ void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset,
		case GSI_VER_2_7:
		maxn = GSI_V2_7_GSI_INST_RAM_n_MAXn;
		break;
		case GSI_VER_2_9:
		maxn = GSI_V2_9_GSI_INST_RAM_n_MAXn;
		break;
		case GSI_VER_ERR:
		case GSI_VER_MAX:
		default:

drivers/platform/msm/gsi/gsi_reg_v2.h

+34 −0

Original line number	Diff line number	Diff line
		@@ -442,6 +442,7 @@
		#define GSI_V2_2_GSI_INST_RAM_n_MAXn 4095
		#define GSI_V2_5_GSI_INST_RAM_n_MAXn 8191
		#define GSI_V2_7_GSI_INST_RAM_n_MAXn 5119
		#define GSI_V2_9_GSI_INST_RAM_n_MAXn 6143

		#define GSI_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000
		#define GSI_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18
		@@ -884,6 +885,39 @@
		#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4
		#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5

		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(n) \
		(GSI_GSI_REG_BASE_OFFS + 0x00012040 + 0x4000 * (n))
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_MAXn 2
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_INI(n) \
		in_dword_masked(GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(n), \
		GSI_V2_9_EE_n_GSI_HW_PARAM_2_RMSK)
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_INMI(n, mask) \
		in_dword_masked(GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(n), \
		mask)
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7f80000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
		#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0

		#define GSI_EE_n_GSI_SW_VERSION_OFFS(n) \
		(GSI_GSI_REG_BASE_OFFS + 0x00012044 + 0x4000 * (n))
		#define GSI_EE_n_GSI_SW_VERSION_MAJOR_BMSK 0xf0000000

drivers/platform/msm/ipa/ipa_api.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -3082,6 +3082,9 @@ const char *ipa_get_version_string(enum ipa_hw_type ver)
		case IPA_HW_v4_7:
		str = "4.7";
		break;
		case IPA_HW_v4_9:
		str = "4.9";
		break;
		default:
		str = "Invalid version";
		break;
		@@ -3192,6 +3195,7 @@ static int ipa_generic_plat_drv_probe(struct platform_device *pdev_p)
		case IPA_HW_v4_2:
		case IPA_HW_v4_5:
		case IPA_HW_v4_7:
		case IPA_HW_v4_9:
		result = ipa3_plat_drv_probe(pdev_p, ipa_api_ctrl,
		ipa_plat_drv_match);
		break;

drivers/platform/msm/ipa/ipa_v3/ipa.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -5450,6 +5450,9 @@ static enum gsi_ver ipa3_get_gsi_ver(enum ipa_hw_type ipa_hw_type)
		case IPA_HW_v4_7:
		gsi_ver = GSI_VER_2_7;
		break;
		case IPA_HW_v4_9:
		gsi_ver = GSI_VER_2_9;
		break;
		default:
		IPAERR("No GSI version for ipa type %d\n", ipa_hw_type);
		WARN_ON(1);

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+226 −1

Original line number	Diff line number	Diff line
		@@ -178,6 +178,10 @@
		#define IPA_v4_7_SRC_GROUP_MAX (1)
		#define IPA_v4_7_DST_GROUP_MAX (1)

		#define IPA_v4_9_GROUP_UL_DL (0)
		#define IPA_v4_9_SRC_GROUP_MAX (1)
		#define IPA_v4_9_DST_GROUP_MAX (1)

		#define IPA_GROUP_MAX IPA_v3_0_GROUP_MAX

		enum ipa_rsrc_grp_type_src {
		@@ -253,6 +257,7 @@ enum ipa_ver {
		IPA_4_5_MHI,
		IPA_4_5_APQ,
		IPA_4_7,
		IPA_4_9,
		IPA_VER_MAX,
		};

		@@ -421,6 +426,19 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
		{15, 15}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		},
		[IPA_4_9] = {
		/* UL_DL other are invalid */
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
		{1, 12}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = {
		{20, 20}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {
		{38, 38}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {
		{0, 4}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
		{30, 30}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		},

		};

		@@ -512,6 +530,13 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config
		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
		{2, 2}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		},
		[IPA_4_9] = {
		/* UL/DL/DPL, other are invalid */
		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
		{9, 9}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
		{2, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		},

		};

		@@ -577,6 +602,11 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config
		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
		{3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		},
		[IPA_4_9] = {
		/* unused UL_DL unused unused UC_RX_Q N/A */
		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
		{3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
		},

		};

		@@ -656,6 +686,7 @@ static const struct ipa_qmb_outstanding ipa3_qmb_outstanding
		[IPA_4_5_APQ][IPA_QMB_INSTANCE_DDR] = {16, 8},
		[IPA_4_5_APQ][IPA_QMB_INSTANCE_PCIE] = {12, 8},
		[IPA_4_7][IPA_QMB_INSTANCE_DDR] = {13, 12},
		[IPA_4_9][IPA_QMB_INSTANCE_DDR] = {16, 8},
		};

		struct ipa_ep_configuration {
		@@ -2879,6 +2910,161 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
		QMB_MASTER_SELECT_DDR,
		{ 31, 31, 8, 8, IPA_EE_AP } },

		/* IPA_4_9 */
		[IPA_4_9][IPA_CLIENT_USB_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		true,
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_APPS_WAN_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		true,
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 2, 2, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 8 } },
		[IPA_4_9][IPA_CLIENT_WLAN1_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		true,
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 3, 3, 8, 16, IPA_EE_AP, GSI_FREE_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_APPS_LAN_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 4, 4, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_WIGIG_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		true,
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 9, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
		[IPA_4_9][IPA_CLIENT_APPS_CMD_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
		QMB_MASTER_SELECT_DDR,
		{ 7, 6, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_Q6_WAN_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		true,
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_Q6_CMD_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = {
		true, IPA_v4_9_GROUP_UL_DL,
		true,
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,
		QMB_MASTER_SELECT_DDR,
		{ 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } },


		[IPA_4_9][IPA_CLIENT_APPS_WAN_COAL_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 19, 11, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
		[IPA_4_9][IPA_CLIENT_APPS_WAN_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 20, 12, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_USB_DPL_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 21, 13, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_ODL_DPL_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 22, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_WIGIG1_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 23, 15, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_WLAN1_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 24, 16, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
		[IPA_4_9][IPA_CLIENT_USB_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 25, 17, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_WIGIG2_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 26, 18, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_WIGIG3_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 27, 19, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_WIGIG4_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 28, 20, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_APPS_LAN_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 11, 7, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_Q6_LAN_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 12, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 13, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },
		[IPA_4_9][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 14, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 15, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },
		[IPA_4_9][IPA_CLIENT_Q6_WAN_CONS] = {
		true, IPA_v4_9_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 16, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },


		};

		static struct ipa3_mem_partition ipa_4_1_mem_part = {
		@@ -3664,6 +3850,9 @@ static u8 ipa3_get_hw_type_index(void)
		case IPA_HW_v4_7:
		hw_type_index = IPA_4_7;
		break;
		case IPA_HW_v4_9:
		hw_type_index = IPA_4_9;
		break;
		default:
		IPAERR("Incorrect IPA version %d\n", ipa3_ctx->ipa_hw_type);
		hw_type_index = IPA_3_0;
		@@ -5607,6 +5796,7 @@ int ipa3_init_mem_partition(enum ipa_hw_type type)
		ipa3_ctx->ctrl->mem_partition = &ipa_4_5_mem_part;
		break;
		case IPA_HW_v4_7:
		case IPA_HW_v4_9:
		ipa3_ctx->ctrl->mem_partition = &ipa_4_7_mem_part;
		break;
		case IPA_HW_None:
		@@ -7321,6 +7511,35 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index,
		}
		}
		break;
		case IPA_4_9:
		if (src) {
		switch (group_index) {
		case IPA_v4_9_GROUP_UL_DL:
		ipahal_write_reg_n_fields(
		IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n,
		n, val);
		break;
		default:
		IPAERR(
		" Invalid source resource group,index #%d\n",
		group_index);
		break;
		}
		} else {
		switch (group_index) {
		case IPA_v4_9_GROUP_UL_DL:
		ipahal_write_reg_n_fields(
		IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,
		n, val);
		break;
		default:
		IPAERR(
		" Invalid destination resource group,index #%d\n",
		group_index);
		break;
		}
		}
		break;

		default:
		IPAERR("invalid hw type\n");
		@@ -7479,6 +7698,12 @@ void ipa3_set_resorce_groups_min_max_limits(void)
		src_grp_idx_max = IPA_v4_7_SRC_GROUP_MAX;
		dst_grp_idx_max = IPA_v4_7_DST_GROUP_MAX;
		break;
		case IPA_4_9:
		src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX;
		dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX;
		src_grp_idx_max = IPA_v4_9_SRC_GROUP_MAX;
		dst_grp_idx_max = IPA_v4_9_DST_GROUP_MAX;
		break;
		default:
		IPAERR("invalid hw type index\n");
		WARN_ON(1);