Loading msm/sde/sde_core_irq.c +6 −3 Original line number Diff line number Diff line Loading @@ -475,8 +475,11 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms) return; for (i = 0; i < sde_kms->irq_obj.total_irqs; i++) { if (sde_kms->irq_obj.irq_cb_tbl) INIT_LIST_HEAD(&sde_kms->irq_obj.irq_cb_tbl[i]); if (sde_kms->irq_obj.enable_counts) atomic_set(&sde_kms->irq_obj.enable_counts[i], 0); if (sde_kms->irq_obj.irq_counts) atomic_set(&sde_kms->irq_obj.irq_counts[i], 0); } } Loading msm/sde/sde_crtc.c +23 −1 Original line number Diff line number Diff line Loading @@ -4562,8 +4562,10 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, struct sde_crtc *sde_crtc; struct plane_state *pstates = NULL; struct sde_crtc_state *cstate; const struct drm_plane_state *pstate; struct drm_plane *plane; struct drm_display_mode *mode; int rc = 0; int mixer_height, mixer_width, rc = 0; struct sde_multirect_plane_states *multirect_plane = NULL; struct drm_connector *conn; struct drm_connector_list_iter conn_iter; Loading Loading @@ -4620,6 +4622,26 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, } drm_connector_list_iter_end(&conn_iter); mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode); mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode); if (cstate->num_ds_enabled) { if (!state->state) goto end; drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { if ((pstate->crtc_h > mixer_height) || (pstate->crtc_w > mixer_width)) { SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n", pstate->crtc_w, pstate->crtc_h, mixer_width, mixer_height); return -E2BIG; goto end; } } } _sde_crtc_setup_is_ppsplit(state); _sde_crtc_setup_lm_bounds(crtc, state); Loading msm/sde/sde_encoder.c +8 −4 Original line number Diff line number Diff line Loading @@ -3099,7 +3099,11 @@ void sde_encoder_virt_restore(struct drm_encoder *drm_enc) sde_enc = to_sde_encoder_virt(drm_enc); if (sde_enc->cur_master) if (!sde_enc->cur_master) { SDE_ERROR("virt encoder has no master\n"); return; } memset(&sde_enc->cur_master->intf_cfg_v1, 0, sizeof(sde_enc->cur_master->intf_cfg_v1)); sde_enc->idle_pc_restore = true; Loading @@ -3117,7 +3121,7 @@ void sde_encoder_virt_restore(struct drm_encoder *drm_enc) phys->ops.restore(phys); } if (sde_enc->cur_master && sde_enc->cur_master->ops.restore) if (sde_enc->cur_master->ops.restore) sde_enc->cur_master->ops.restore(sde_enc->cur_master); _sde_encoder_virt_enable_helper(drm_enc); Loading msm/sde/sde_hw_reg_dma_v1_color_proc.c +2 −1 Original line number Diff line number Diff line Loading @@ -2764,13 +2764,14 @@ void reg_dmav1_setup_scaler3_lut(struct sde_reg_dma_setup_ops_cfg *buf, + off_tbl[filter][i][1]; lut_len = off_tbl[filter][i][0] << 2; REG_DMA_SETUP_OPS(*buf, lut_addr, &lut[filter][0], lut_len * sizeof(u32), &lut[filter][lut_offset], lut_len * sizeof(u32), REG_BLK_WRITE_SINGLE, 0, 0, 0); rc = dma_ops->setup_payload(buf); if (rc) { DRM_ERROR("lut write failed ret %d\n", rc); return; } lut_offset += lut_len; } } Loading msm/sde/sde_hw_sspp.c +2 −1 Original line number Diff line number Diff line Loading @@ -158,11 +158,12 @@ static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx, u32 *idx) { int rc = 0; const struct sde_sspp_sub_blks *sblk = ctx->cap->sblk; const struct sde_sspp_sub_blks *sblk; if (!ctx) return -EINVAL; sblk = ctx->cap->sblk; switch (s_id) { case SDE_SSPP_SRC: *idx = sblk->src_blk.base; Loading Loading
msm/sde/sde_core_irq.c +6 −3 Original line number Diff line number Diff line Loading @@ -475,8 +475,11 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms) return; for (i = 0; i < sde_kms->irq_obj.total_irqs; i++) { if (sde_kms->irq_obj.irq_cb_tbl) INIT_LIST_HEAD(&sde_kms->irq_obj.irq_cb_tbl[i]); if (sde_kms->irq_obj.enable_counts) atomic_set(&sde_kms->irq_obj.enable_counts[i], 0); if (sde_kms->irq_obj.irq_counts) atomic_set(&sde_kms->irq_obj.irq_counts[i], 0); } } Loading
msm/sde/sde_crtc.c +23 −1 Original line number Diff line number Diff line Loading @@ -4562,8 +4562,10 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, struct sde_crtc *sde_crtc; struct plane_state *pstates = NULL; struct sde_crtc_state *cstate; const struct drm_plane_state *pstate; struct drm_plane *plane; struct drm_display_mode *mode; int rc = 0; int mixer_height, mixer_width, rc = 0; struct sde_multirect_plane_states *multirect_plane = NULL; struct drm_connector *conn; struct drm_connector_list_iter conn_iter; Loading Loading @@ -4620,6 +4622,26 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, } drm_connector_list_iter_end(&conn_iter); mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode); mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode); if (cstate->num_ds_enabled) { if (!state->state) goto end; drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { if ((pstate->crtc_h > mixer_height) || (pstate->crtc_w > mixer_width)) { SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n", pstate->crtc_w, pstate->crtc_h, mixer_width, mixer_height); return -E2BIG; goto end; } } } _sde_crtc_setup_is_ppsplit(state); _sde_crtc_setup_lm_bounds(crtc, state); Loading
msm/sde/sde_encoder.c +8 −4 Original line number Diff line number Diff line Loading @@ -3099,7 +3099,11 @@ void sde_encoder_virt_restore(struct drm_encoder *drm_enc) sde_enc = to_sde_encoder_virt(drm_enc); if (sde_enc->cur_master) if (!sde_enc->cur_master) { SDE_ERROR("virt encoder has no master\n"); return; } memset(&sde_enc->cur_master->intf_cfg_v1, 0, sizeof(sde_enc->cur_master->intf_cfg_v1)); sde_enc->idle_pc_restore = true; Loading @@ -3117,7 +3121,7 @@ void sde_encoder_virt_restore(struct drm_encoder *drm_enc) phys->ops.restore(phys); } if (sde_enc->cur_master && sde_enc->cur_master->ops.restore) if (sde_enc->cur_master->ops.restore) sde_enc->cur_master->ops.restore(sde_enc->cur_master); _sde_encoder_virt_enable_helper(drm_enc); Loading
msm/sde/sde_hw_reg_dma_v1_color_proc.c +2 −1 Original line number Diff line number Diff line Loading @@ -2764,13 +2764,14 @@ void reg_dmav1_setup_scaler3_lut(struct sde_reg_dma_setup_ops_cfg *buf, + off_tbl[filter][i][1]; lut_len = off_tbl[filter][i][0] << 2; REG_DMA_SETUP_OPS(*buf, lut_addr, &lut[filter][0], lut_len * sizeof(u32), &lut[filter][lut_offset], lut_len * sizeof(u32), REG_BLK_WRITE_SINGLE, 0, 0, 0); rc = dma_ops->setup_payload(buf); if (rc) { DRM_ERROR("lut write failed ret %d\n", rc); return; } lut_offset += lut_len; } } Loading
msm/sde/sde_hw_sspp.c +2 −1 Original line number Diff line number Diff line Loading @@ -158,11 +158,12 @@ static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx, u32 *idx) { int rc = 0; const struct sde_sspp_sub_blks *sblk = ctx->cap->sblk; const struct sde_sspp_sub_blks *sblk; if (!ctx) return -EINVAL; sblk = ctx->cap->sblk; switch (s_id) { case SDE_SSPP_SRC: *idx = sblk->src_blk.base; Loading