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Commit 135a2f38 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v4.8-rockchip-dts64-1' of... 

Merge tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

The rk3399 gets support for its emmc controller as well as thermal,
i2c and core io-domain nodes and some reasonable default rates
for core clocks. The rk3368 also gets io-domains for its r88 board
as well as a small fix for the gic's memory regions.

* tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

:
  arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
  arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
  arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
  arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
  arm64: dts: rockchip: add i2c nodes for rk3399
  arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
  arm64: dts: rockchip: add rk3399 io-domain core nodes
  arm64: dts: rockchip: add rk3368-r88 iodomains
  arm64: dts: rockchip: add rk3368 io-domain core nodes
  arm64: dts: rockchip: make rk3368 grf syscons simple-mfds
  arm64: dts: rockchip: enable eMMC for rk3399 EVB
  arm64: dts: rockchip: add sdhci/emmc for rk3399
  arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
  arm64: dts: rockchip: assign default rates for core rk3399 clocks

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7f95b51d 5d26ad9c

arch/arm64/boot/dts/rockchip/rk3368-r88.dts

+16 −0
Original line number Diff line number Diff line
@@ -236,6 +236,15 @@ 
	};

};



&io_domains {

	status = "ok";



	audio-supply = <&vcc_io>;

	gpio30-supply = <&vcc_io>;

	gpio1830-supply = <&vcc_io>;

	wifi-supply = <&vccio_wl>;

};



&sdio0 {

	assigned-clocks = <&cru SCLK_SDIO0>;

	assigned-clock-parents = <&cru PLL_CPLL>;
@@ -329,6 +338,13 @@ 
	};

};



&pmu_io_domains {

	status = "okay";



	pmu-supply = <&vcc_io>;

	vop-supply = <&vcc_io>;

};



&saradc {

	vref-supply = <&vcc_18>;

	status = "okay";

arch/arm64/boot/dts/rockchip/rk3368.dtsi

+13 −3
Original line number Diff line number Diff line
@@ -632,8 +632,13 @@ 
	};



	pmugrf: syscon@ff738000 {

		compatible = "rockchip,rk3368-pmugrf", "syscon";

		compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";

		reg = <0x0 0xff738000 0x0 0x1000>;



		pmu_io_domains: io-domains {

			compatible = "rockchip,rk3368-pmu-io-voltage-domain";

			status = "disabled";

		};

	};



	cru: clock-controller@ff760000 {
@@ -645,8 +650,13 @@ 
	};



	grf: syscon@ff770000 {

		compatible = "rockchip,rk3368-grf", "syscon";

		compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";

		reg = <0x0 0xff770000 0x0 0x1000>;



		io_domains: io-domains {

			compatible = "rockchip,rk3368-io-voltage-domain";

			status = "disabled";

		};

	};



	wdt: watchdog@ff800000 {
@@ -670,7 +680,7 @@ 
		#address-cells = <0>;



		reg = <0x0 0xffb71000 0x0 0x1000>,

		      <0x0 0xffb72000 0x0 0x1000>,

		      <0x0 0xffb72000 0x0 0x2000>,

		      <0x0 0xffb74000 0x0 0x2000>,

		      <0x0 0xffb76000 0x0 0x2000>;

		interrupts = <GIC_PPI 9

arch/arm64/boot/dts/rockchip/rk3399-evb.dts

+12 −0
Original line number Diff line number Diff line
@@ -77,6 +77,10 @@ 
	};

};



&emmc_phy {

	status = "okay";

};



&pwm0 {

	status = "okay";

};
@@ -89,6 +93,14 @@ 
	status = "okay";

};



&sdhci {

	bus-width = <8>;

	mmc-hs400-1_8v;

	mmc-hs400-enhanced-strobe;

	non-removable;

	status = "okay";

};



&uart2 {

	status = "okay";

};

arch/arm64/boot/dts/rockchip/rk3399.dtsi

+311 −2
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/pinctrl/rockchip.h>

#include <dt-bindings/thermal/thermal.h>



/ {

	compatible = "rockchip,rk3399";
@@ -54,6 +55,15 @@ 
	#size-cells = <2>;



	aliases {

		i2c0 = &i2c0;

		i2c1 = &i2c1;

		i2c2 = &i2c2;

		i2c3 = &i2c3;

		i2c4 = &i2c4;

		i2c5 = &i2c5;

		i2c6 = &i2c6;

		i2c7 = &i2c7;

		i2c8 = &i2c8;

		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &uart2;
@@ -215,6 +225,22 @@ 
		status = "disabled";

	};



	sdhci: sdhci@fe330000 {

		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";

		reg = <0x0 0xfe330000 0x0 0x10000>;

		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

		arasan,soc-ctl-syscon = <&grf>;

		assigned-clocks = <&cru SCLK_EMMC>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;

		clock-names = "clk_xin", "clk_ahb";

		clock-output-names = "emmc_cardclock";

		#clock-cells = <0>;

		phys = <&emmc_phy>;

		phy-names = "phy_arasan";

		status = "disabled";

	};



	usb_host0_ehci: usb@fe380000 {

		compatible = "generic-ehci";

		reg = <0x0 0xfe380000 0x0 0x20000>;
@@ -272,6 +298,96 @@ 
		};

	};



	i2c1: i2c@ff110000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff110000 0x0 0x1000>;

		assigned-clocks = <&cru SCLK_I2C1>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c1_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	i2c2: i2c@ff120000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff120000 0x0 0x1000>;

		assigned-clocks = <&cru SCLK_I2C2>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c2_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	i2c3: i2c@ff130000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff130000 0x0 0x1000>;

		assigned-clocks = <&cru SCLK_I2C3>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c3_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	i2c5: i2c@ff140000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff140000 0x0 0x1000>;

		assigned-clocks = <&cru SCLK_I2C5>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c5_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	i2c6: i2c@ff150000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff150000 0x0 0x1000>;

		assigned-clocks = <&cru SCLK_I2C6>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c6_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	i2c7: i2c@ff160000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff160000 0x0 0x1000>;

		assigned-clocks = <&cru SCLK_I2C7>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c7_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	uart0: serial@ff180000 {

		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";

		reg = <0x0 0xff180000 0x0 0x100>;
@@ -389,9 +505,105 @@ 
		status = "disabled";

	};



	thermal-zones {

		cpu_thermal: cpu {

			polling-delay-passive = <100>;

			polling-delay = <1000>;



			thermal-sensors = <&tsadc 0>;



			trips {

				cpu_alert0: cpu_alert0 {

					temperature = <70000>;

					hysteresis = <2000>;

					type = "passive";

				};

				cpu_alert1: cpu_alert1 {

					temperature = <75000>;

					hysteresis = <2000>;

					type = "passive";

				};

				cpu_crit: cpu_crit {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&cpu_alert0>;

					cooling-device =

						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

				map1 {

					trip = <&cpu_alert1>;

					cooling-device =

						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};



		gpu_thermal: gpu {

			polling-delay-passive = <100>;

			polling-delay = <1000>;



			thermal-sensors = <&tsadc 1>;



			trips {

				gpu_alert0: gpu_alert0 {

					temperature = <75000>;

					hysteresis = <2000>;

					type = "passive";

				};

				gpu_crit: gpu_crit {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&gpu_alert0>;

					cooling-device =

						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};

	};



	tsadc: tsadc@ff260000 {

		compatible = "rockchip,rk3399-tsadc";

		reg = <0x0 0xff260000 0x0 0x100>;

		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

		assigned-clocks = <&cru SCLK_TSADC>;

		assigned-clock-rates = <750000>;

		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;

		clock-names = "tsadc", "apb_pclk";

		resets = <&cru SRST_TSADC>;

		reset-names = "tsadc-apb";

		rockchip,grf = <&grf>;

		rockchip,hw-tshut-temp = <95000>;

		pinctrl-names = "init", "default", "sleep";

		pinctrl-0 = <&otp_gpio>;

		pinctrl-1 = <&otp_out>;

		pinctrl-2 = <&otp_gpio>;

		#thermal-sensor-cells = <1>;

		status = "disabled";

	};



	pmugrf: syscon@ff320000 {

		compatible = "rockchip,rk3399-pmugrf", "syscon";

		compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";

		reg = <0x0 0xff320000 0x0 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		pmu_io_domains: io-domains {

			compatible = "rockchip,rk3399-pmu-io-voltage-domain";

			status = "disabled";

		};

	};



	spi3: spi@ff350000 {
@@ -420,6 +632,51 @@ 
		status = "disabled";

	};



	i2c0: i2c@ff3c0000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff3c0000 0x0 0x1000>;

		assigned-clocks = <&pmucru SCLK_I2C0_PMU>;

		assigned-clock-rates = <200000000>;

		clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c0_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	i2c4: i2c@ff3d0000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff3d0000 0x0 0x1000>;

		assigned-clocks = <&pmucru SCLK_I2C4_PMU>;

		assigned-clock-rates = <200000000>;

		clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c4_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	i2c8: i2c@ff3e0000 {

		compatible = "rockchip,rk3399-i2c";

		reg = <0x0 0xff3e0000 0x0 0x1000>;

		assigned-clocks = <&pmucru SCLK_I2C8_PMU>;

		assigned-clock-rates = <200000000>;

		clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;

		clock-names = "i2c", "pclk";

		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c8_xfer>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	pwm0: pwm@ff420000 {

		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";

		reg = <0x0 0xff420000 0x0 0x10>;
@@ -478,11 +735,43 @@ 
		reg = <0x0 0xff760000 0x0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		assigned-clocks =

			<&cru PLL_GPLL>, <&cru PLL_CPLL>,

			<&cru PLL_NPLL>,

			<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,

			<&cru PCLK_PERIHP>,

			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,

			<&cru PCLK_PERILP0>,

			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;

		assigned-clock-rates =

			 <594000000>,  <800000000>,

			<1000000000>,

			 <150000000>,   <75000000>,

			  <37500000>,

			 <100000000>,  <100000000>,

			  <50000000>,

			 <100000000>,   <50000000>;

	};



	grf: syscon@ff770000 {

		compatible = "rockchip,rk3399-grf", "syscon";

		compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";

		reg = <0x0 0xff770000 0x0 0x10000>;

		#address-cells = <1>;

		#size-cells = <1>;



		io_domains: io-domains {

			compatible = "rockchip,rk3399-io-voltage-domain";

			status = "disabled";

		};



		emmc_phy: phy@f780 {

			compatible = "rockchip,rk3399-emmc-phy";

			reg = <0xf780 0x24>;

			clocks = <&sdhci>;

			clock-names = "emmcclk";

			#phy-cells = <0>;

			status = "disabled";

		};

	};



	watchdog@ff840000 {
@@ -756,6 +1045,16 @@ 
			};

		};



		sleep {

			ap_pwroff: ap-pwroff {

				rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;

			};



			ddrio_pwroff: ddrio-pwroff {

				rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;

			};

		};



		spdif {

			spdif_bus: spdif-bus {

				rockchip,pins =
@@ -881,6 +1180,16 @@ 
			};

		};



		tsadc {

			otp_gpio: otp-gpio {

				rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;

			};



			otp_out: otp-out {

				rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;

			};

		};



		uart0 {

			uart0_xfer: uart0-xfer {

				rockchip,pins =