Loading bindings/ufs/ufs-qcom.txt +4 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,10 @@ Optional properties: - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply - resets : specifies the PHY reset in the UFS controller - limit-rate : specifies if the rate has to be limited to A or B. 1 = rate B, 0 = rate A. 1 = rate A, 2 = rate B. - limit-phy-submode : specifies the PHY submode which is used for PHY calibration, 0 = non-G4, 1 = G4. Example: ufsphy1: ufsphy@fc597000 { Loading qcom/lahaina-rumi.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -27,7 +27,7 @@ &ufshc_mem { limit-tx-hs-gear = <1>; limit-rx-hs-gear = <1>; limit-rate = <1>; limit-rate = <2>; /* HS Rate-B */ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; Loading qcom/lahaina.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1422,6 +1422,7 @@ phys = <&ufsphy_mem>; phy-names = "ufsphy"; lanes-per-direction = <2>; limit-rate = <1>; /* HS Rate-A */ dev-ref-clk-freq = <0>; /* 19.2 MHz */ clock-names = Loading Loading
bindings/ufs/ufs-qcom.txt +4 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,10 @@ Optional properties: - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply - resets : specifies the PHY reset in the UFS controller - limit-rate : specifies if the rate has to be limited to A or B. 1 = rate B, 0 = rate A. 1 = rate A, 2 = rate B. - limit-phy-submode : specifies the PHY submode which is used for PHY calibration, 0 = non-G4, 1 = G4. Example: ufsphy1: ufsphy@fc597000 { Loading
qcom/lahaina-rumi.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -27,7 +27,7 @@ &ufshc_mem { limit-tx-hs-gear = <1>; limit-rx-hs-gear = <1>; limit-rate = <1>; limit-rate = <2>; /* HS Rate-B */ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; Loading
qcom/lahaina.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1422,6 +1422,7 @@ phys = <&ufsphy_mem>; phy-names = "ufsphy"; lanes-per-direction = <2>; limit-rate = <1>; /* HS Rate-A */ dev-ref-clk-freq = <0>; /* 19.2 MHz */ clock-names = Loading