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Commit 11e71007 authored by Jon Hunter's avatar Jon Hunter Committed by Greg Kroah-Hartman
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serial: tegra: Add delay after enabling FIFO mode 



For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 3 UART clock periods after enabling
the TX fifo, otherwise data could be lost.

Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 245c0278

drivers/tty/serial/serial-tegra.c

+10 −0
Original line number Diff line number Diff line
@@ -885,6 +885,16 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) 
	tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;

	tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);



	/* Dummy read to ensure the write is posted */

	tegra_uart_read(tup, UART_SCR);



	/*

	 * For all tegra devices (up to t210), there is a hardware issue that

	 * requires software to wait for 3 UART clock periods after enabling

	 * the TX fifo, otherwise data could be lost.

	 */

	tegra_uart_wait_cycle_time(tup, 3);



	/*

	 * Initialize the UART with default configuration

	 * (115200, N, 8, 1) so that the receive DMA buffer may be