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Commit 1179cd69 authored by Marijn Suijten's avatar Marijn Suijten Committed by Greg Kroah-Hartman
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ARM: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL reference



[ Upstream commit f1db21c315f4b4f8c3fbea56aac500673132d317 ]

The 28NM DSI PLL driver for msm8960 calculates with a 27MHz reference
clock and should hence use PXO, not CXO which runs at 19.2MHz.

Note that none of the DSI PHY/PLL drivers currently use this "ref"
clock; they all rely on (sometimes inexistant) global clock names and
usually function normally without a parent clock.  This discrepancy will
be corrected in a future patch, for which this change needs to be in
place first.

Fixes: 6969d1d9 ("ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY")
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829203027.276143-2-marijn.suijten@somainline.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent bdc189d6
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+2 −2
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@
			clock-frequency = <19200000>;
		};

		pxo_board {
		pxo_board: pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
@@ -1304,7 +1304,7 @@
			reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
			clock-names = "iface_clk", "ref";
			clocks = <&mmcc DSI_M_AHB_CLK>,
				 <&cxo_board>;
				 <&pxo_board>;
		};