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Commit 10e0744a authored by Shreyas K K's avatar Shreyas K K Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add mem-dump and CPU dump nodes to SM6150 

Add mem-dump and CPU memory dump nodes to SM6150.

Change-Id: If38e0285007e59b35ade8f74d3a983b08a802562
parent 06b9ee95

qcom/sm6150.dtsi

+210 −130
Original line number Diff line number Diff line
@@ -65,20 +65,6 @@ 
				      cache-level = <3>;

				};

			};



			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_0: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU1: cpu@100 {
@@ -98,20 +84,6 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_100: l1-tlb {

				qcom,dump-size = <0x5000>;

			};

		};
@@ -132,20 +104,6 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_200: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_200: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_200: l1-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU3: cpu@300 {
@@ -165,20 +123,6 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_300: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_300: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_300: l1-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU4: cpu@400 {
@@ -198,20 +142,6 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_400: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_400: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_400: l1-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU5: cpu@500 {
@@ -231,20 +161,6 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_500: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_500: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_500: l1-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU6: cpu@600 {
@@ -263,29 +179,6 @@ 
			      cache-size = <0x40000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			      qcom,dump-size = <0x48000>;

			};



			L1_I_600: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x11000>;

			};



			L1_D_600: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};



			L1_ITLB_600: l1-itlb {

				qcom,dump-size = <0x300>;

			};



			L1_DTLB_600: l1-dtlb {

				qcom,dump-size = <0x480>;

			};



			L2_TLB_600: l2-tlb {

				qcom,dump-size = <0x7800>;

			};

		};
@@ -305,29 +198,6 @@ 
			      cache-size = <0x40000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			      qcom,dump-size = <0x48000>;

			};



			L1_I_700: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x11000>;

			};



			L1_D_700: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};



			L1_ITLB_700: l1-itlb {

				qcom,dump-size = <0x300>;

			};



			L1_DTLB_700: l1-dtlb {

				qcom,dump-size = <0x480>;

			};



			L2_TLB_700: l2-tlb {

				qcom,dump-size = <0x7800>;

			};

		};
@@ -1008,6 +878,216 @@ 
		cap-based-alloc-and-pwr-collapse;

	};



	mem_dump {

		compatible = "qcom,mem-dump";

		memory-region = <&dump_mem>;



		rpmh {

			qcom,dump-size = <0x2000000>;

			qcom,dump-id = <0xec>;

		};



		rpm_sw {

			qcom,dump-size = <0x28000>;

			qcom,dump-id = <0xea>;

		};



		pmic {

			qcom,dump-size = <0x10000>;

			qcom,dump-id = <0xe4>;

		};



		fcm {

			qcom,dump-size = <0x8400>;

			qcom,dump-id = <0xee>;

		};



		tmc_etf {

			qcom,dump-size = <0x8000>;

			qcom,dump-id = <0xf0>;

		};



		etf_swao {

			qcom,dump-size = <0x8000>;

			qcom,dump-id = <0xf1>;

		};



		etr_reg {

			qcom,dump-size = <0x1000>;

			qcom,dump-id = <0x100>;

		};



		etf_reg {

			qcom,dump-size = <0x1000>;

			qcom,dump-id = <0x101>;

		};



		etfswao_reg {

			qcom,dump-size = <0x1000>;

			qcom,dump-id = <0x102>;

		};



		misc_data {

			qcom,dump-size = <0x1000>;

			qcom,dump-id = <0xe8>;

		};



		l1_icache0 {

			qcom,dump-size = <0x8800>;

			qcom,dump-id = <0x60>;

		};



		l1_icache100 {

			qcom,dump-size = <0x8800>;

			qcom,dump-id = <0x61>;

		};



		l1_icache200 {

			qcom,dump-size = <0x8800>;

			qcom,dump-id = <0x62>;

		};



		l1_icache300 {

			qcom,dump-size = <0x8800>;

			qcom,dump-id = <0x63>;

		};



		l1_icache400 {

			qcom,dump-size = <0x8800>;

			qcom,dump-id = <0x64>;

		};



		l1_icache500 {

			qcom,dump-size = <0x8800>;

			qcom,dump-id = <0x65>;

		};



		l1_icache600 {

			qcom,dump-size = <0x11000>;

			qcom,dump-id = <0x66>;

		};



		l1_icache700 {

			qcom,dump-size = <0x11000>;

			qcom,dump-id = <0x67>;

		};



		l1_dcache0 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x80>;

		};



		l1_dcache100 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x81>;

		};



		l1_dcache200 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x82>;

		};



		l1_dcache300 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x83>;

		};



		l1_dcache400 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x84>;

		};



		l1_dcache500 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x85>;

		};



		l1_dcache600 {

			qcom,dump-size = <0x12000>;

			qcom,dump-id = <0x86>;

		};



		l1_dcache700 {

			qcom,dump-size = <0x12000>;

			qcom,dump-id = <0x87>;

		};



		l1_itlb600 {

			qcom,dump-size = <0x300>;

			qcom,dump-id = <0x26>;

		};



		l1_itlb700 {

			qcom,dump-size = <0x300>;

			qcom,dump-id = <0x27>;

		};



		l1_dtlb600 {

			qcom,dump-size = <0x480>;

			qcom,dump-id = <0x46>;

		};



		l1_dtlb700 {

			qcom,dump-size = <0x480>;

			qcom,dump-id = <0x47>;

		};



		l2_cache600 {

			qcom,dump-size = <0x48000>;

			qcom,dump-id = <0xc6>;

		};



		l2_cache700 {

			qcom,dump-size = <0x48000>;

			qcom,dump-id = <0xc7>;

		};



		l2_tlb0 {

			qcom,dump-size = <0x5000>;

			qcom,dump-id = <0x120>;

		};



		l2_tlb100 {

			qcom,dump-size = <0x5000>;

			qcom,dump-id = <0x121>;

		};



		l2_tlb200 {

			qcom,dump-size = <0x5000>;

			qcom,dump-id = <0x122>;

		};



		l2_tlb300 {

			qcom,dump-size = <0x5000>;

			qcom,dump-id = <0x123>;

		};



		l2_tlb400 {

			qcom,dump-size = <0x5000>;

			qcom,dump-id = <0x124>;

		};



		l2_tlb500 {

			qcom,dump-size = <0x5000>;

			qcom,dump-id = <0x125>;

		};



		l2_tlb600 {

			qcom,dump-size = <0x7800>;

			qcom,dump-id = <0x126>;

		};



		l2_tlb700 {

			qcom,dump-size = <0x7800>;

			qcom,dump-id = <0x127>;

		};



		llcc1_d_cache {

			qcom,dump-size = <0x6c000>;

			qcom,dump-id = <0x140>;

		};

	};



	apps_rsc: rsc@18200000 {

		label = "apps_rsc";

		compatible = "qcom,rpmh-rsc";