Loading qcom/lahaina.dtsi +0 −3 Original line number Diff line number Diff line Loading @@ -2347,7 +2347,6 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; Loading @@ -2360,7 +2359,6 @@ reg-names = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; Loading @@ -2372,7 +2370,6 @@ reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; Loading Loading
qcom/lahaina.dtsi +0 −3 Original line number Diff line number Diff line Loading @@ -2347,7 +2347,6 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; Loading @@ -2360,7 +2359,6 @@ reg-names = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; Loading @@ -2372,7 +2370,6 @@ reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; Loading