Loading qcom/lahaina.dtsi +15 −0 Original line number Diff line number Diff line Loading @@ -2317,6 +2317,21 @@ qcom,pil-size = <0x0F0000>; // padding to 960 KB status = "ok"; }; eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; interrupt-parent = <&pdc>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x088E0000 0x2000>, <0x088E2000 0x1000>; reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-clock-vote-req; clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>; clock-names = "eud_ahb2phy_clk"; status = "ok"; }; }; #include "lahaina-regulators.dtsi" Loading Loading
qcom/lahaina.dtsi +15 −0 Original line number Diff line number Diff line Loading @@ -2317,6 +2317,21 @@ qcom,pil-size = <0x0F0000>; // padding to 960 KB status = "ok"; }; eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; interrupt-parent = <&pdc>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x088E0000 0x2000>, <0x088E2000 0x1000>; reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-clock-vote-req; clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>; clock-names = "eud_ahb2phy_clk"; status = "ok"; }; }; #include "lahaina-regulators.dtsi" Loading