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Commit 105cf3c8 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI updates from Bjorn Helgaas:

 - skip AER driver error recovery callbacks for correctable errors
   reported via ACPI APEI, as we already do for errors reported via the
   native path (Tyler Baicar)

 - fix DPC shared interrupt handling (Alex Williamson)

 - print full DPC interrupt number (Keith Busch)

 - enable DPC only if AER is available (Keith Busch)

 - simplify DPC code (Bjorn Helgaas)

 - calculate ASPM L1 substate parameter instead of hardcoding it (Bjorn
   Helgaas)

 - enable Latency Tolerance Reporting for ASPM L1 substates (Bjorn
   Helgaas)

 - move ASPM internal interfaces out of public header (Bjorn Helgaas)

 - allow hot-removal of VGA devices (Mika Westerberg)

 - speed up unplug and shutdown by assuming Thunderbolt controllers
   don't support Command Completed events (Lukas Wunner)

 - add AtomicOps support for GPU and Infiniband drivers (Felix Kuehling,
   Jay Cornwall)

 - expose "ari_enabled" in sysfs to help NIC naming (Stuart Hayes)

 - clean up PCI DMA interface usage (Christoph Hellwig)

 - remove PCI pool API (replaced with DMA pool) (Romain Perier)

 - deprecate pci_get_bus_and_slot(), which assumed PCI domain 0 (Sinan
   Kaya)

 - move DT PCI code from drivers/of/ to drivers/pci/ (Rob Herring)

 - add PCI-specific wrappers for dev_info(), etc (Frederick Lawler)

 - remove warnings on sysfs mmap failure (Bjorn Helgaas)

 - quiet ROM validation messages (Alex Deucher)

 - remove redundant memory alloc failure messages (Markus Elfring)

 - fill in types for compile-time VGA and other I/O port resources
   (Bjorn Helgaas)

 - make "pci=pcie_scan_all" work for Root Ports as well as Downstream
   Ports to help AmigaOne X1000 (Bjorn Helgaas)

 - add SPDX tags to all PCI files (Bjorn Helgaas)

 - quirk Marvell 9128 DMA aliases (Alex Williamson)

 - quirk broken INTx disable on Ceton InfiniTV4 (Bjorn Helgaas)

 - fix CONFIG_PCI=n build by adding dummy pci_irqd_intx_xlate() (Niklas
   Cassel)

 - use DMA API to get MSI address for DesignWare IP (Niklas Cassel)

 - fix endpoint-mode DMA mask configuration (Kishon Vijay Abraham I)

 - fix ARTPEC-6 incorrect IS_ERR() usage (Wei Yongjun)

 - add support for ARTPEC-7 SoC (Niklas Cassel)

 - add endpoint-mode support for ARTPEC (Niklas Cassel)

 - add Cadence PCIe host and endpoint controller driver (Cyrille
   Pitchen)

 - handle multiple INTx status bits being set in dra7xx (Vignesh R)

 - translate dra7xx hwirq range to fix INTD handling (Vignesh R)

 - remove deprecated Exynos PHY initialization code (Jaehoon Chung)

 - fix MSI erratum workaround for HiSilicon Hip06/Hip07 (Dongdong Liu)

 - fix NULL pointer dereference in iProc BCMA driver (Ray Jui)

 - fix Keystone interrupt-controller-node lookup (Johan Hovold)

 - constify qcom driver structures (Julia Lawall)

 - rework Tegra config space mapping to increase space available for
   endpoints (Vidya Sagar)

 - simplify Tegra driver by using bus->sysdata (Manikanta Maddireddy)

 - remove PCI_REASSIGN_ALL_BUS usage on Tegra (Manikanta Maddireddy)

 - add support for Global Fabric Manager Server (GFMS) event to
   Microsemi Switchtec switch driver (Logan Gunthorpe)

 - add IDs for Switchtec PSX 24xG3 and PSX 48xG3 (Kelvin Cao)

* tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (140 commits)
  PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller
  dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller
  PCI: endpoint: Fix EPF device name to support multi-function devices
  PCI: endpoint: Add the function number as argument to EPC ops
  PCI: cadence: Add host driver for Cadence PCIe controller
  dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe host controller
  PCI: Add vendor ID for Cadence
  PCI: Add generic function to probe PCI host controllers
  PCI: generic: fix missing call of pci_free_resource_list()
  PCI: OF: Add generic function to parse and allocate PCI resources
  PCI: Regroup all PCI related entries into drivers/pci/Makefile
  PCI/DPC: Reformat DPC register definitions
  PCI/DPC: Add and use DPC Status register field definitions
  PCI/DPC: Squash dpc_rp_pio_get_info() into dpc_process_rp_pio_error()
  PCI/DPC: Remove unnecessary RP PIO register structs
  PCI/DPC: Push dpc->rp_pio_status assignment into dpc_rp_pio_get_info()
  PCI/DPC: Squash dpc_rp_pio_print_error() into dpc_rp_pio_get_info()
  PCI/DPC: Make RP PIO log size check more generic
  PCI/DPC: Rename local "status" to "dpc_status"
  PCI/DPC: Squash dpc_rp_pio_print_tlp_header() into dpc_rp_pio_print_error()
  ...
parents e237f98a ab8c6093

Documentation/admin-guide/kernel-parameters.txt

+5 −1
Original line number Diff line number Diff line
@@ -3711,7 +3711,11 @@ 
			[KNL, SMP] Set scheduler's default relax_domain_level.

			See Documentation/cgroup-v1/cpusets.txt.



	reserve=	[KNL,BUGS] Force the kernel to ignore some iomem area

	reserve=	[KNL,BUGS] Force kernel to ignore I/O ports or memory

			Format: <base1>,<size1>[,<base2>,<size2>,...]

			Reserve I/O ports or memory so the kernel won't use

			them.  If <base> is less than 0x10000, the region

			is assumed to be I/O ports; otherwise it is memory.



	reservetop=	[X86-32]

			Format: nn[KMG]

Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt

+4 −1
Original line number Diff line number Diff line
@@ -4,7 +4,10 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP 
and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "axis,artpec6-pcie", "snps,dw-pcie"

- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;

	      "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;

	      "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;

	      "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;

- reg: base addresses and lengths of the PCIe controller (DBI),

	the PHY controller, and configuration address space.

- reg-names: Must include the following entries:

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
* Cadence PCIe endpoint controller



Required properties:

- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.

- reg: Should contain the controller register base address and AXI interface

  region base address respectively.

- reg-names: Must be "reg" and "mem" respectively.

- cdns,max-outbound-regions: Set to maximum number of outbound regions



Optional properties:

- max-functions: Maximum number of functions that can be configured (default 1).



Example:



pcie@fc000000 {

	compatible = "cdns,cdns-pcie-ep";

	reg = <0x0 0xfc000000 0x0 0x01000000>,

	      <0x0 0x80000000 0x0 0x40000000>;

	reg-names = "reg", "mem";

	cdns,max-outbound-regions = <16>;

	max-functions = /bits/ 8 <8>;

};

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt

0 → 100644
+60 −0
Original line number Diff line number Diff line 
* Cadence PCIe host controller



This PCIe controller inherits the base properties defined in

host-generic-pci.txt.



Required properties:

- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.

- reg: Should contain the controller register base address, PCIe configuration

  window base address, and AXI interface region base address respectively.

- reg-names: Must be "reg", "cfg" and "mem" respectively.

- #address-cells: Set to <3>

- #size-cells: Set to <2>

- device_type: Set to "pci"

- ranges: Ranges for the PCI memory and I/O regions

- #interrupt-cells: Set to <1>

- interrupt-map-mask and interrupt-map: Standard PCI properties to define the

  mapping of the PCIe interface to interrupt numbers.



Optional properties:

- cdns,max-outbound-regions: Set to maximum number of outbound regions

  (default 32)

- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the

  number of least significant bits kept during inbound (PCIe -> AXI) address

  translations (default 32)

- vendor-id: The PCI vendor ID (16 bits, default is design dependent)

- device-id: The PCI device ID (16 bits, default is design dependent)



Example:



pcie@fb000000 {

	compatible = "cdns,cdns-pcie-host";

	device_type = "pci";

	#address-cells = <3>;

	#size-cells = <2>;

	bus-range = <0x0 0xff>;

	linux,pci-domain = <0>;

	cdns,max-outbound-regions = <16>;

	cdns,no-bar-match-nbits = <32>;

	vendor-id = /bits/ 16 <0x17cd>;

	device-id = /bits/ 16 <0x0200>;



	reg = <0x0 0xfb000000  0x0 0x01000000>,

	      <0x0 0x41000000  0x0 0x00001000>,

	      <0x0 0x40000000  0x0 0x04000000>;

	reg-names = "reg", "cfg", "mem";



	ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,

		 <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;



	#interrupt-cells = <0x1>;



	interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1

			 0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1

			 0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1

			 0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;



	interrupt-map-mask = <0x0 0x0 0x0  0x7>;



	msi-parent = <&its_pci>;

};

Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt

+11 −47
Original line number Diff line number Diff line
@@ -6,9 +6,6 @@ and thus inherits all the common properties defined in designware-pcie.txt. 
Required properties:

- compatible: "samsung,exynos5440-pcie"

- reg: base addresses and lengths of the PCIe controller,

	the PHY controller, additional register for the PHY controller.

	(Registers for the PHY controller are DEPRECATED.

	 Use the PHY framework.)

- reg-names : First name should be set to "elbi".

	And use the "config" instead of getting the configuration address space

	from "ranges".
@@ -23,49 +20,8 @@ For other common properties, refer to 


Example:



SoC-specific DT Entry:

SoC-specific DT Entry (with using PHY framework):



	pcie@290000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000

			0x270000 0x1000

			0x271000 0x40>;

		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



	pcie@2a0000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x2a0000 0x1000

			0x272000 0x1000

			0x271040 0x40>;

		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;

		clocks = <&clock 29>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



With using PHY framework:

	pcie_phy0: pcie-phy@270000 {

		...

		reg = <0x270000 0x1000>, <0x271000 0x40>;
@@ -74,13 +30,21 @@ With using PHY framework: 
	};



	pcie@290000 {

		...

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000>, <0x40000000 0x1000>;

		reg-names = "elbi", "config";

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		phys = <&pcie_phy0>;

		ranges = <0x81000000 0 0	  0x60001000 0 0x00010000

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;

		...

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



Board-specific DT Entry: