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Commit 1053e6bb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'core-iommu-for-linus' of... 

Merge branch 'core-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'core-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86/amd-iommu: Update copyright headers
  x86/amd-iommu: Reenable AMD IOMMU if it's mysteriously vanished over suspend
  AGP: Warn when GATT memory cannot be set to UC
  x86, GART: Disable GART table walk probes
  x86, GART: Remove superfluous AMD64_GARTEN
parents a8fe1500 3d8a1a6a

arch/x86/include/asm/amd_iommu.h

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.

 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.

 * Author: Joerg Roedel <joerg.roedel@amd.com>

 *         Leo Duran <leo.duran@amd.com>

 *

arch/x86/include/asm/amd_iommu_proto.h

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2009 Advanced Micro Devices, Inc.

 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.

 * Author: Joerg Roedel <joerg.roedel@amd.com>

 *

 * This program is free software; you can redistribute it and/or modify it

arch/x86/include/asm/amd_iommu_types.h

+16 −7
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.

 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.

 * Author: Joerg Roedel <joerg.roedel@amd.com>

 *         Leo Duran <leo.duran@amd.com>

 *
@@ -416,13 +416,22 @@ struct amd_iommu { 
	struct dma_ops_domain *default_dom;



	/*

	 * This array is required to work around a potential BIOS bug.

	 * The BIOS may miss to restore parts of the PCI configuration

	 * space when the system resumes from S3. The result is that the

	 * IOMMU does not execute commands anymore which leads to system

	 * failure.

	 * We can't rely on the BIOS to restore all values on reinit, so we

	 * need to stash them

	 */

	u32 cache_cfg[4];



	/* The iommu BAR */

	u32 stored_addr_lo;

	u32 stored_addr_hi;



	/*

	 * Each iommu has 6 l1s, each of which is documented as having 0x12

	 * registers

	 */

	u32 stored_l1[6][0x12];



	/* The l2 indirect registers */

	u32 stored_l2[0x83];

};



/*

arch/x86/include/asm/gart.h

+14 −1
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ extern int fix_aperture; 
#define GARTEN		(1<<0)

#define DISGARTCPU	(1<<4)

#define DISGARTIO	(1<<5)

#define DISTLBWALKPRB	(1<<6)



/* GART cache control register bits. */

#define INVGART		(1<<0)
@@ -27,7 +28,6 @@ extern int fix_aperture; 
#define AMD64_GARTAPERTUREBASE	0x94

#define AMD64_GARTTABLEBASE	0x98

#define AMD64_GARTCACHECTL	0x9c

#define AMD64_GARTEN		(1<<0)



#ifdef CONFIG_GART_IOMMU

extern int gart_iommu_aperture;
@@ -57,6 +57,19 @@ static inline void gart_iommu_hole_init(void) 


extern int agp_amd64_init(void);



static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)

{

	u32 ctl;



	/*

	 * Don't enable translation but enable GART IO and CPU accesses.

	 * Also, set DISTLBWALKPRB since GART tables memory is UC.

	 */

	ctl = DISTLBWALKPRB | order << 1;



	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);

}



static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)

{

	u32 tmp, ctl;

arch/x86/kernel/amd_iommu.c

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.

 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.

 * Author: Joerg Roedel <joerg.roedel@amd.com>

 *         Leo Duran <leo.duran@amd.com>

 *